soc/intel/apollolake: Bypass FSP's deassertion of PERST# signal.
BUG=b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I1858c7843d16b6b63fc30762a889916bbb9b781a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25311 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -304,6 +304,17 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
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die("Can not find SoC devicetree\n");
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m_cfg->PrmrrSize = config->PrmrrSize;
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/* FSP performs a PERST# signal deassertion for PCIe ports with
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* the GPIO address specified in these UPDs. Over-ride the default
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* addresses with 0 to bypass PERST# signal deassertion in FSP.
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*/
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m_cfg->RootPort0Perst = 0;
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m_cfg->RootPort1Perst = 0;
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m_cfg->RootPort2Perst = 0;
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m_cfg->RootPort3Perst = 0;
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m_cfg->RootPort4Perst = 0;
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m_cfg->RootPort5Perst = 0;
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#endif
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}
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