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soc/intel/cannonlake/acpi: Replace Store(a,b) with ASL 2.0 syntax 

Replace `Store (a, b)` with `b = a`.

Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Felix Singer 2022-12-12 07:36:41 +01:00
parent 8cc2962b12
commit 3dc4d84586
4 changed files with 42 additions and 42 deletions
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36
src/soc/intel/cannonlake/acpi/gpio.asl
View File

@ -30,20 +30,20 @@ Device (GPIO)
/* GPIO Community 0 */ /* GPIO Community 0 */
CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
CreateDWordField (^RBUF, ^COM0._LEN, LEN0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
Store (^^PCRB (PID_GPIOCOM0), BAS0) BAS0 = ^^PCRB (PID_GPIOCOM0)
Store (GPIO_BASE_SIZE, LEN0) LEN0 = GPIO_BASE_SIZE
/* GPIO Community 1 */ /* GPIO Community 1 */
CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
CreateDWordField (^RBUF, ^COM1._LEN, LEN1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
Store (^^PCRB (PID_GPIOCOM1), BAS1) BAS1 = ^^PCRB (PID_GPIOCOM1)
Store (GPIO_BASE_SIZE, LEN1) LEN1 = GPIO_BASE_SIZE
/* GPIO Community 4 */ /* GPIO Community 4 */
CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
CreateDWordField (^RBUF, ^COM4._LEN, LEN4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
Store (^^PCRB (PID_GPIOCOM4), BAS4) BAS4 = ^^PCRB (PID_GPIOCOM4)
Store (GPIO_BASE_SIZE, LEN4) LEN4 = GPIO_BASE_SIZE
Return (RBUF) Return (RBUF)
} }
@ -63,34 +63,34 @@ Method (GADD, 1, NotSerialized)
/* GPIO Community 0 */ /* GPIO Community 0 */
If (Arg0 >= GPP_A0 && Arg0 <= SPI0_CLK_LOOPBK) If (Arg0 >= GPP_A0 && Arg0 <= SPI0_CLK_LOOPBK)
{ {
Store (PID_GPIOCOM0, Local0) Local0 = PID_GPIOCOM0
Local1 = Arg0 - GPP_A0 Local1 = Arg0 - GPP_A0
} }
/* GPIO Community 1 */ /* GPIO Community 1 */
If (Arg0 >= GPP_D0 && Arg0 <= vSD3_CD_B) If (Arg0 >= GPP_D0 && Arg0 <= vSD3_CD_B)
{ {
Store (PID_GPIOCOM1, Local0) Local0 = PID_GPIOCOM1
Local1 = Arg0 - GPP_D0 Local1 = Arg0 - GPP_D0
} }
/* GPIO Community 2 */ /* GPIO Community 2 */
If (Arg0 >= GPD0 && Arg0 <= DRAM_RESET_B) If (Arg0 >= GPD0 && Arg0 <= DRAM_RESET_B)
{ {
Store (PID_GPIOCOM2, Local0) Local0 = PID_GPIOCOM2
Local1 = Arg0 - GPD0 Local1 = Arg0 - GPD0
} }
/* GPIO Community 3 */ /* GPIO Community 3 */
If (Arg0 >= HDA_BCLK && Arg0 <= TRIGGER_OUT) If (Arg0 >= HDA_BCLK && Arg0 <= TRIGGER_OUT)
{ {
Store (PID_GPIOCOM3, Local0) Local0 = PID_GPIOCOM3
Local1 = Arg0 - HDA_BCLK Local1 = Arg0 - HDA_BCLK
} }
/* GPIO Community 4*/ /* GPIO Community 4*/
If (Arg0 >= GPP_C0 && Arg0 <= CL_RST_B) If (Arg0 >= GPP_C0 && Arg0 <= CL_RST_B)
{ {
Store (PID_GPIOCOM4, Local0) Local0 = PID_GPIOCOM4
Local1 = Arg0 - GPP_C0 Local1 = Arg0 - GPP_C0
} }
Store (PCRB (Local0), Local2) Local2 = PCRB (Local0)
Local2 += PAD_CFG_BASE Local2 += PAD_CFG_BASE
Return (Local2 + Local1 * 16) Return (Local2 + Local1 * 16)
} }
@ -105,19 +105,19 @@ Method (GPID, 1, Serialized)
Switch (ToInteger (Arg0)) Switch (ToInteger (Arg0))
{ {
Case (0) { Case (0) {
Store (PID_GPIOCOM0, Local0) Local0 = PID_GPIOCOM0
} }
Case (1) { Case (1) {
Store (PID_GPIOCOM1, Local0) Local0 = PID_GPIOCOM1
} }
Case (2) { Case (2) {
Store (PID_GPIOCOM2, Local0) Local0 = PID_GPIOCOM2
} }
Case (3) { Case (3) {
Store (PID_GPIOCOM3, Local0) Local0 = PID_GPIOCOM3
} }
Case (4) { Case (4) {
Store (PID_GPIOCOM4, Local0) Local0 = PID_GPIOCOM4
} }
Default { Default {
Return (0) Return (0)
@ -135,7 +135,7 @@ Method (GPID, 1, Serialized)
*/ */
Method (CGPM, 2, Serialized) Method (CGPM, 2, Serialized)
{ {
Store (GPID (Arg0), Local0) Local0 = GPID (Arg0)
If (Local0 != 0) { If (Local0 != 0) {
/* Mask off current PM bits */ /* Mask off current PM bits */
PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_GPIO_PM_CONFIG_BITS)) PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_GPIO_PM_CONFIG_BITS))

26
src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl
View File

@ -30,26 +30,26 @@ Device (GPIO)
/* GPIO Community 0 */ /* GPIO Community 0 */
CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
CreateDWordField (^RBUF, ^COM0._LEN, LEN0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
Store (^^PCRB (PID_GPIOCOM0), BAS0) BAS0 = ^^PCRB (PID_GPIOCOM0)
Store (GPIO_BASE_SIZE, LEN0) LEN0 = GPIO_BASE_SIZE
/* GPIO Community 1 */ /* GPIO Community 1 */
CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
CreateDWordField (^RBUF, ^COM1._LEN, LEN1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
Store (^^PCRB (PID_GPIOCOM1), BAS1) BAS1 = ^^PCRB (PID_GPIOCOM1)
Store (GPIO_BASE_SIZE, LEN1) LEN1 = GPIO_BASE_SIZE
/* GPIO Community 3 */ /* GPIO Community 3 */
CreateDWordField (^RBUF, ^COM3._BAS, BAS3) CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
CreateDWordField (^RBUF, ^COM3._LEN, LEN3) CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
Store (^^PCRB (PID_GPIOCOM3), BAS3) BAS3 = ^^PCRB (PID_GPIOCOM3)
Store (GPIO_BASE_SIZE, LEN3) LEN3 = GPIO_BASE_SIZE
/* GPIO Community 4 */ /* GPIO Community 4 */
CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
CreateDWordField (^RBUF, ^COM4._LEN, LEN4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
Store (^^PCRB (PID_GPIOCOM4), BAS4) BAS4 = ^^PCRB (PID_GPIOCOM4)
Store (GPIO_BASE_SIZE, LEN4) LEN4 = GPIO_BASE_SIZE
Return (RBUF) Return (RBUF)
} }
@ -69,28 +69,28 @@ Method (GADD, 1, NotSerialized)
/* GPIO Community 0 */ /* GPIO Community 0 */
If (Arg0 >= GPP_A0 && Arg0 <= GSPI1_CLK_LOOPBK) If (Arg0 >= GPP_A0 && Arg0 <= GSPI1_CLK_LOOPBK)
{ {
Store (PID_GPIOCOM0, Local0) Local0 = PID_GPIOCOM0
Local1 = Arg0 - GPP_A0 Local1 = Arg0 - GPP_A0
} }
/* GPIO Community 1 */ /* GPIO Community 1 */
If (Arg0 >= GPP_C0 && Arg0 <= vSSP2_RXD) If (Arg0 >= GPP_C0 && Arg0 <= vSSP2_RXD)
{ {
Store (PID_GPIOCOM1, Local0) Local0 = PID_GPIOCOM1
Local1 = Arg0 - GPP_C0 Local1 = Arg0 - GPP_C0
} }
/* GPIO Community 3*/ /* GPIO Community 3*/
If (Arg0 >= GPP_K0 && Arg0 <= SPI0_CLK_LOOPBK) If (Arg0 >= GPP_K0 && Arg0 <= SPI0_CLK_LOOPBK)
{ {
Store (PID_GPIOCOM3, Local0) Local0 = PID_GPIOCOM3
Local1 = Arg0 - GPP_K0 Local1 = Arg0 - GPP_K0
} }
/* GPIO Community 4*/ /* GPIO Community 4*/
If (Arg0 >= HDACPU_SDI && Arg0 <= GPP_J11) If (Arg0 >= HDACPU_SDI && Arg0 <= GPP_J11)
{ {
Store (PID_GPIOCOM4, Local0) Local0 = PID_GPIOCOM4
Local1 = Arg0 - GPP_I0 Local1 = Arg0 - GPP_I0
} }
Store (PCRB (Local0), Local2) Local2 = PCRB (Local0)
Local2 += PAD_CFG_BASE Local2 += PAD_CFG_BASE
Return (Local2 + Local1 * 16) Return (Local2 + Local1 * 16)
} }

6
src/soc/intel/cannonlake/acpi/pch_hda.asl
View File

@ -55,9 +55,9 @@ Device (HDAS)
CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
CreateQWordField (NBUF, ^NHLT._LEN, NLEN) CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
Store (NHLA, NBAS) NBAS = NHLA
Store (NHLA, NMAS) NMAS = NHLA
Store (NHLL, NLEN) NLEN = NHLL
Return (NBUF) Return (NBUF)
} }

16
src/soc/intel/cannonlake/acpi/scs.asl
View File

@ -39,22 +39,22 @@ Scope (\_SB.PCI0) {
Method(_PS0, 0, Serialized) { Method(_PS0, 0, Serialized) {
Stall (50) // Sleep 50 us Stall (50) // Sleep 50 us
Store(0, PGEN) // Disable PG PGEN = 0 // Disable PG
/* Clear register 0x1C20/0x4820 */ /* Clear register 0x1C20/0x4820 */
^^SCSC (PID_EMMC) ^^SCSC (PID_EMMC)
/* Set Power State to D0 */ /* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR) And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP) ^TEMP = PMCR
} }
Method(_PS3, 0, Serialized) { Method(_PS3, 0, Serialized) {
Store(1, PGEN) // Enable PG PGEN = 1 // Enable PG
/* Set Power State to D3 */ /* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR) Or (PMCR, 0x0003, PMCR)
Store (PMCR, ^TEMP) ^TEMP = PMCR
} }
Device (CARD) Device (CARD)
@ -203,14 +203,14 @@ Scope (\_SB.PCI0) {
Method (_PS0, 0, Serialized) Method (_PS0, 0, Serialized)
{ {
Store (0, PGEN) /* Disable PG */ PGEN = 0 /* Disable PG */
/* Clear register 0x1C20/0x4820 */ /* Clear register 0x1C20/0x4820 */
^^SCSC (PID_SDX) ^^SCSC (PID_SDX)
/* Set Power State to D0 */ /* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR) And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP) ^TEMP = PMCR
#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) #if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
/* Change pad mode to Native */ /* Change pad mode to Native */
@ -220,11 +220,11 @@ Scope (\_SB.PCI0) {
Method (_PS3, 0, Serialized) Method (_PS3, 0, Serialized)
{ {
Store (1, PGEN) /* Enable PG */ PGEN = 1 /* Enable PG */
/* Set Power State to D3 */ /* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR) Or (PMCR, 0x0003, PMCR)
Store (PMCR, ^TEMP) ^TEMP = PMCR
#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) #if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
/* Change pad mode to GPIO control */ /* Change pad mode to GPIO control */