nb/i945: Improve code formatting
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS
Nico Huber
parent
fd8de1860d
commit
3dff32c804
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@ -40,9 +40,9 @@ Device (PDRC)
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
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@ -10,16 +10,13 @@ void bootblock_early_northbridge_init(void)
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uint32_t reg;
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/*
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true.
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* That way all subsequent non-explicit config accesses use
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
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* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
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* because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit
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* config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final assumption is that
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* no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
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*/
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
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@ -10,9 +10,7 @@
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void print_pci_devices(void)
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{
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pci_devfn_t dev;
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for (dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0, 0, 1)) {
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for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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@ -30,7 +28,8 @@ void dump_pci_device(unsigned int dev)
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{
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int i;
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printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
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printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f,
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(dev >> 12) & 7);
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for (i = 0; i <= 255; i++) {
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unsigned char val;
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@ -46,9 +45,7 @@ void dump_pci_device(unsigned int dev)
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void dump_pci_devices(void)
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{
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pci_devfn_t dev;
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for (dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0, 0, 1)) {
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for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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@ -1,15 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <arch/io.h>
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#include <cbmem.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cbmem.h>
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#include <romstage_handoff.h>
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#include <device/pci_ops.h>
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#include <device/pci.h>
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#include <option.h>
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#include <romstage_handoff.h>
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#include <types.h>
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#include "i945.h"
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@ -41,8 +41,8 @@ static void i945m_detect_chipset(void)
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case 6:
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printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
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break;
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default:
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printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */
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default: /* Others reserved. */
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printk(BIOS_INFO, "Unknown (%02x)", reg8);
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}
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printk(BIOS_INFO, " Chipset\n");
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@ -75,8 +75,8 @@ static void i945m_detect_chipset(void)
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case 4:
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printk(BIOS_DEBUG, "DDR2-400");
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break;
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default:
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printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
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default: /* Others reserved. */
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printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);
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}
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printk(BIOS_DEBUG, "\n");
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@ -90,7 +90,8 @@ static void i945_detect_chipset(void)
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printk(BIOS_INFO, "\nIntel(R) ");
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reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
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reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4)
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| ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
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switch (reg8) {
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case 0:
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case 1:
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@ -125,8 +126,8 @@ static void i945_detect_chipset(void)
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case 3:
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printk(BIOS_DEBUG, "up to DDR2-533");
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break;
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default:
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printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
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default: /* Others reserved. */
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printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);
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}
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printk(BIOS_DEBUG, "\n");
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@ -403,9 +404,9 @@ static void i945_setup_dmi_rcrb(void)
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reg32 = DMIBAR32(0x204);
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reg32 &= ~0x3ff;
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#if 1
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reg32 |= 0x13f; /* for x4 DMI only */
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reg32 |= 0x13f; /* for x4 DMI only */
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#else
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reg32 |= 0x1e4; /* for x2 DMI only */
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reg32 |= 0x1e4; /* for x2 DMI only */
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#endif
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DMIBAR32(0x204) = reg32;
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@ -543,8 +544,7 @@ static void i945_setup_pci_express_x16(void)
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pci_write_config16(p2peg, PEG_CAP, reg16);
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/* Setup SLOTCAP */
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/* TODO: These values are mainboard dependent and should
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* be set from devicetree.cb.
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/* TODO: These values are mainboard dependent and should be set from devicetree.cb.
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*/
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/* NOTE: SLOTCAP becomes RO after the first write! */
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reg32 = pci_read_config32(p2peg, SLOTCAP);
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@ -701,9 +701,8 @@ static void i945_setup_pci_express_x16(void)
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if (i945_silicon_revision() >= 3) {
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static const u32 reglist[] = {
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0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24,
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0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c,
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0xfb0, 0xfc4, 0xfd8, 0xfec
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0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, 0xf38, 0xf4c,
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0xf60, 0xf74, 0xf88, 0xf9c, 0xfb0, 0xfc4, 0xfd8, 0xfec
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};
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int i;
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@ -96,8 +96,7 @@ static void mch_domain_read_resources(struct device *dev)
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delta_cbmem = tomk_stolen - cbmem_topk;
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tomk_stolen -= delta_cbmem;
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printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n",
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delta_cbmem);
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printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem);
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/* The following needs to be 2 lines, otherwise the second
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@ -263,8 +263,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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/* clear self refresh status if check is disabled or not a resume */
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if (!CONFIG(CHECK_SLFRCS_ON_RESUME)
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|| sysinfo->boot_path != BOOT_PATH_RESUME) {
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if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) {
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MCHBAR8(SLFRCS) |= 3;
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} else {
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/* Validate self refresh config */
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@ -300,8 +299,7 @@ struct timings {
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/**
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* @brief loop over dimms and save maximal timings
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*/
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static void gather_common_timing(struct sys_info *sysinfo,
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struct timings *saved_timings)
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static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings)
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{
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int i, j;
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@ -310,8 +308,8 @@ static void gather_common_timing(struct sys_info *sysinfo,
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memset(saved_timings, 0, sizeof(*saved_timings));
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saved_timings->max_tRR = UINT32_MAX;
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saved_timings->cas_mask = SPD_CAS_LATENCY_DDR2_3
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| SPD_CAS_LATENCY_DDR2_4 | SPD_CAS_LATENCY_DDR2_5;
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saved_timings->cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4
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| SPD_CAS_LATENCY_DDR2_5;
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/**
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* i945 supports two DIMMs, in two configurations:
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@ -388,8 +386,7 @@ static void gather_common_timing(struct sys_info *sysinfo,
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if (spd_dimm_is_registered_ddr2(dimm_info.dimm_type))
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die("\nError: Registered memory not supported by this chipset\n");
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printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1),
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(i & 1));
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printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
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/**
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* There are 5 different possible populations for a DIMM socket:
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* 0. x16 double ranked (X16DS)
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@ -442,8 +439,7 @@ static void gather_common_timing(struct sys_info *sysinfo,
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die("DDR-II rank size smaller than 128MB is not supported.\n");
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sysinfo->banksize[i * 2] = dimm_info.ranksize_mb / 32;
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printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i,
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sysinfo->banksize[i * 2] * 32);
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printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32);
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if (dimm_info.ranks == 2) {
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sysinfo->banksize[(i * 2) + 1] =
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dimm_info.ranksize_mb / 32;
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@ -457,25 +453,18 @@ static void gather_common_timing(struct sys_info *sysinfo,
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sysinfo->banks[i] = dimm_info.banks;
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/* int min_tRAS, min_tRP, min_tRCD, min_tWR, min_tRFC; */
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saved_timings->min_tRAS = MAX(saved_timings->min_tRAS,
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dimm_info.tRAS);
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saved_timings->min_tRP = MAX(saved_timings->min_tRP,
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dimm_info.tRP);
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saved_timings->min_tRCD = MAX(saved_timings->min_tRCD,
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dimm_info.tRCD);
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saved_timings->min_tWR = MAX(saved_timings->min_tWR,
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dimm_info.tWR);
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saved_timings->min_tRFC = MAX(saved_timings->min_tRFC,
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dimm_info.tRFC);
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saved_timings->max_tRR = MIN(saved_timings->max_tRR,
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dimm_info.tRR);
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saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, dimm_info.tRAS);
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saved_timings->min_tRP = MAX(saved_timings->min_tRP, dimm_info.tRP);
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saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, dimm_info.tRCD);
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saved_timings->min_tWR = MAX(saved_timings->min_tWR, dimm_info.tWR);
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saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, dimm_info.tRFC);
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saved_timings->max_tRR = MIN(saved_timings->max_tRR, dimm_info.tRR);
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saved_timings->cas_mask &= dimm_info.cas_supported;
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for (j = 0; j < 8; j++) {
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if (!(saved_timings->cas_mask & (1 << j)))
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saved_timings->min_tCLK_cas[j] = 0;
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else
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saved_timings->min_tCLK_cas[j] =
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MAX(dimm_info.cycle_time[j],
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saved_timings->min_tCLK_cas[j] = MAX(dimm_info.cycle_time[j],
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saved_timings->min_tCLK_cas[j]);
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}
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dimm_mask |= (1 << i);
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@ -488,14 +477,12 @@ static void gather_common_timing(struct sys_info *sysinfo,
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printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
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}
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static void choose_tclk(struct sys_info *sysinfo,
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struct timings *saved_timings)
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static void choose_tclk(struct sys_info *sysinfo, struct timings *saved_timings)
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{
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u32 ctrl_min_tclk;
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int try_cas;
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ctrl_min_tclk = 2 * 256 * 1000
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/ sdram_capabilities_max_supported_memory_frequency();
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ctrl_min_tclk = 2 * 256 * 1000 / sdram_capabilities_max_supported_memory_frequency();
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normalize_tck(&ctrl_min_tclk);
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try_cas = spd_get_msbs(saved_timings->cas_mask);
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@ -504,8 +491,8 @@ static void choose_tclk(struct sys_info *sysinfo,
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sysinfo->cas = try_cas;
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sysinfo->tclk = saved_timings->min_tCLK_cas[try_cas];
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if (sysinfo->tclk >= ctrl_min_tclk &&
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saved_timings->min_tCLK_cas[try_cas] !=
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saved_timings->min_tCLK_cas[try_cas - 1])
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saved_timings->min_tCLK_cas[try_cas] !=
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saved_timings->min_tCLK_cas[try_cas - 1])
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break;
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try_cas--;
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}
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@ -539,8 +526,7 @@ static void choose_tclk(struct sys_info *sysinfo,
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sysinfo->memory_frequency, sysinfo->cas);
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}
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static void derive_timings(struct sys_info *sysinfo,
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struct timings *saved_timings)
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static void derive_timings(struct sys_info *sysinfo, struct timings *saved_timings)
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{
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sysinfo->tras = DIV_ROUND_UP(saved_timings->min_tRAS, sysinfo->tclk);
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if (sysinfo->tras > 0x18)
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@ -961,7 +947,8 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
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/* Channel 0 */
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sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
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sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
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if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED))
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if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) &&
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(sysinfo->package == SYSINFO_PACKAGE_STACKED))
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sdram_write_slew_rates(G3SRPUT, ctl3220);
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else
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@ -1005,20 +992,26 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
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if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
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switch (sysinfo->memory_frequency) {
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case 400:
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channeldll = 0x26262626; break;
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channeldll = 0x26262626;
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break;
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case 533:
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channeldll = 0x22222222; break;
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channeldll = 0x22222222;
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break;
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case 667:
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channeldll = 0x11111111; break;
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channeldll = 0x11111111;
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break;
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}
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} else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
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switch (sysinfo->memory_frequency) {
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case 400:
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channeldll = 0x33333333; break;
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channeldll = 0x33333333;
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break;
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case 533:
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channeldll = 0x24242424; break;
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channeldll = 0x24242424;
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break;
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case 667:
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channeldll = 0x25252525; break;
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channeldll = 0x25252525;
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break;
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}
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}
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@ -1054,7 +1047,6 @@ static void sdram_force_rcomp(void)
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reg8 = i945_silicon_revision();
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if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
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reg32 = MCHBAR32(GBRCOMPCTL);
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reg32 |= (3 << 5);
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||||
MCHBAR32(GBRCOMPCTL) = reg32;
|
||||
|
|
@ -1131,14 +1123,14 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
|
|||
|
||||
/* Is channel 0 populated? */
|
||||
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
|
||||
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
|
||||
reg32 |= (1 << 7) | (1 << 5);
|
||||
else
|
||||
reg32 |= (1 << 31);
|
||||
|
||||
/* Is channel 1 populated? */
|
||||
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
|
||||
reg32 |= (1 << 9) | (1 << 8);
|
||||
else
|
||||
reg32 |= (1 << 30);
|
||||
|
|
@ -1147,13 +1139,13 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
|
|||
|
||||
/* Activate DRAM Channel IO Buffers */
|
||||
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
|
||||
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
|
||||
reg32 = MCHBAR32(C0DRC1);
|
||||
reg32 |= (1 << 8);
|
||||
MCHBAR32(C0DRC1) = reg32;
|
||||
}
|
||||
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
|
||||
reg32 = MCHBAR32(C1DRC1);
|
||||
reg32 |= (1 << 8);
|
||||
MCHBAR32(C1DRC1) = reg32;
|
||||
|
|
@ -1232,20 +1224,24 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
|
|||
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
|
||||
continue;
|
||||
|
||||
columnsrows = (sysinfo->rows[i] & 0x0f)
|
||||
| (sysinfo->cols[i] & 0xf) << 4;
|
||||
columnsrows = (sysinfo->rows[i] & 0x0f) | (sysinfo->cols[i] & 0xf) << 4;
|
||||
|
||||
switch (columnsrows) {
|
||||
case 0x9d:
|
||||
dra = 2; break;
|
||||
dra = 2;
|
||||
break;
|
||||
case 0xad:
|
||||
dra = 3; break;
|
||||
dra = 3;
|
||||
break;
|
||||
case 0xbd:
|
||||
dra = 4; break;
|
||||
dra = 4;
|
||||
break;
|
||||
case 0xae:
|
||||
dra = 3; break;
|
||||
dra = 3;
|
||||
break;
|
||||
case 0xbe:
|
||||
dra = 4; break;
|
||||
dra = 4;
|
||||
break;
|
||||
default:
|
||||
die("Unsupported Rows/Columns. (DRA)");
|
||||
}
|
||||
|
|
@ -1388,8 +1384,7 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
|
|||
reg32 &= ~((1 << 13) | (1 << 12));
|
||||
MCHBAR32(C1DRC0) = reg32;
|
||||
|
||||
if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
|
||||
SYSINFO_DIMM_NOT_POPULATED) {
|
||||
if (!sysinfo->dual_channel && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
|
||||
reg32 = MCHBAR32(C0DRC0);
|
||||
reg32 |= (1 << 15);
|
||||
MCHBAR32(C0DRC0) = reg32;
|
||||
|
|
@ -1491,7 +1486,7 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
|
|||
page_size = 1; /* Default: 1k pagesize */
|
||||
for (i = 0; i < 2*DIMM_SOCKETS; i++) {
|
||||
if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
|
||||
sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
|
||||
sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
|
||||
page_size = 2; /* 2k pagesize */
|
||||
}
|
||||
|
||||
|
|
@ -1568,13 +1563,13 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
|
|||
printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
|
||||
reg32 |= (1 << 1);
|
||||
} else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
|
||||
sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
|
||||
sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
|
||||
/* Channel 1 only */
|
||||
printk(BIOS_DEBUG, "Single Channel 1 only.\n");
|
||||
reg32 |= (1 << 2);
|
||||
} else if (sdram_capabilities_dual_channel() &&
|
||||
(sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) {
|
||||
(sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) {
|
||||
/* Dual Channel Asymmetric */
|
||||
printk(BIOS_DEBUG, "Dual Channel Asymmetric.\n");
|
||||
reg32 |= (1 << 0);
|
||||
|
|
@ -1603,11 +1598,14 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo)
|
|||
/* Only write the lower byte */
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 400:
|
||||
MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
|
||||
MCHBAR8(CPCTL) = 0x90;
|
||||
break;
|
||||
case 533:
|
||||
MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
|
||||
MCHBAR8(CPCTL) = 0x95;
|
||||
break;
|
||||
case 667:
|
||||
MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
|
||||
MCHBAR8(CPCTL) = 0x8d;
|
||||
break;
|
||||
}
|
||||
|
||||
MCHBAR16(CPCTL) &= ~(1 << 11);
|
||||
|
|
@ -1657,11 +1655,14 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
|
|||
freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
|
||||
break;
|
||||
case GFX_FREQUENCY_CAP_250MHZ:
|
||||
freq = CRCLK_250MHz; break;
|
||||
freq = CRCLK_250MHz;
|
||||
break;
|
||||
case GFX_FREQUENCY_CAP_200MHZ:
|
||||
freq = CRCLK_200MHz; break;
|
||||
freq = CRCLK_200MHz;
|
||||
break;
|
||||
case GFX_FREQUENCY_CAP_166MHZ:
|
||||
freq = CRCLK_166MHz; break;
|
||||
freq = CRCLK_166MHz;
|
||||
break;
|
||||
}
|
||||
|
||||
if (freq != CRCLK_400MHz) {
|
||||
|
|
@ -1674,13 +1675,17 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
|
|||
printk(BIOS_DEBUG, "Render: ");
|
||||
switch (freq) {
|
||||
case CRCLK_166MHz:
|
||||
printk(BIOS_DEBUG, "166MHz"); break;
|
||||
printk(BIOS_DEBUG, "166MHz");
|
||||
break;
|
||||
case CRCLK_200MHz:
|
||||
printk(BIOS_DEBUG, "200MHz"); break;
|
||||
printk(BIOS_DEBUG, "200MHz");
|
||||
break;
|
||||
case CRCLK_250MHz:
|
||||
printk(BIOS_DEBUG, "250MHz"); break;
|
||||
printk(BIOS_DEBUG, "250MHz");
|
||||
break;
|
||||
case CRCLK_400MHz:
|
||||
printk(BIOS_DEBUG, "400MHz"); break;
|
||||
printk(BIOS_DEBUG, "400MHz");
|
||||
break;
|
||||
}
|
||||
|
||||
if (i945_silicon_revision() == 0)
|
||||
|
|
@ -1697,8 +1702,8 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
|
|||
u16 fsb = sysinfo->fsb_frequency;
|
||||
|
||||
if ((fsb == 667 && mem == 533) ||
|
||||
(fsb == 533 && mem == 533) ||
|
||||
(fsb == 533 && mem == 400)) {
|
||||
(fsb == 533 && mem == 533) ||
|
||||
(fsb == 533 && mem == 400)) {
|
||||
second_vco = 1;
|
||||
}
|
||||
|
||||
|
|
@ -1764,17 +1769,19 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
|
|||
|
||||
if (sysinfo->clkcfg_bit7) {
|
||||
printk(BIOS_DEBUG, "second VCO, ");
|
||||
|
||||
clkcfg |= (1 << 7);
|
||||
}
|
||||
|
||||
switch (sysinfo->memory_frequency) {
|
||||
case 400:
|
||||
clkcfg |= ((1 + offset) << 4); break;
|
||||
clkcfg |= ((1 + offset) << 4);
|
||||
break;
|
||||
case 533:
|
||||
clkcfg |= ((2 + offset) << 4); break;
|
||||
clkcfg |= ((2 + offset) << 4);
|
||||
break;
|
||||
case 667:
|
||||
clkcfg |= ((3 + offset) << 4); break;
|
||||
clkcfg |= ((3 + offset) << 4);
|
||||
break;
|
||||
default:
|
||||
die("Target Memory Frequency Error");
|
||||
}
|
||||
|
|
@ -1786,9 +1793,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
|
|||
|
||||
MCHBAR32(CLKCFG) = clkcfg;
|
||||
|
||||
/* Make sure the following code is in the
|
||||
* cache before we execute it.
|
||||
*/
|
||||
/* Make sure the following code is in the cache before we execute it. */
|
||||
goto cache_code;
|
||||
vco_update:
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
|
||||
|
|
@ -1929,29 +1934,47 @@ static void sdram_program_clock_crossing(void)
|
|||
printk(BIOS_DEBUG, "MEM=");
|
||||
switch (memclk()) {
|
||||
case 400:
|
||||
printk(BIOS_DEBUG, "400"); idx += 0; break;
|
||||
printk(BIOS_DEBUG, "400");
|
||||
idx += 0;
|
||||
break;
|
||||
case 533:
|
||||
printk(BIOS_DEBUG, "533"); idx += 2; break;
|
||||
printk(BIOS_DEBUG, "533");
|
||||
idx += 2;
|
||||
break;
|
||||
case 667:
|
||||
printk(BIOS_DEBUG, "667"); idx += 4; break;
|
||||
printk(BIOS_DEBUG, "667");
|
||||
idx += 4;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
|
||||
printk(BIOS_DEBUG, "RSVD %x", memclk());
|
||||
return;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, " FSB=");
|
||||
switch (fsbclk()) {
|
||||
case 400:
|
||||
printk(BIOS_DEBUG, "400"); idx += 0; break;
|
||||
printk(BIOS_DEBUG, "400");
|
||||
idx += 0;
|
||||
break;
|
||||
case 533:
|
||||
printk(BIOS_DEBUG, "533"); idx += 6; break;
|
||||
printk(BIOS_DEBUG, "533");
|
||||
idx += 6;
|
||||
break;
|
||||
case 667:
|
||||
printk(BIOS_DEBUG, "667"); idx += 12; break;
|
||||
printk(BIOS_DEBUG, "667");
|
||||
idx += 12;
|
||||
break;
|
||||
case 800:
|
||||
printk(BIOS_DEBUG, "800"); idx += 18; break;
|
||||
printk(BIOS_DEBUG, "800");
|
||||
idx += 18;
|
||||
break;
|
||||
case 1066:
|
||||
printk(BIOS_DEBUG, "1066"); idx += 24; break;
|
||||
printk(BIOS_DEBUG, "1066");
|
||||
idx += 24;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
|
||||
printk(BIOS_DEBUG, "RSVD %x\n", fsbclk());
|
||||
return;
|
||||
}
|
||||
|
||||
if (command_clock_crossing[idx] == 0xffffffff)
|
||||
|
|
@ -2021,9 +2044,9 @@ static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
|
|||
bool chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
|
||||
|
||||
chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
|
||||
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
|
||||
chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED);
|
||||
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED);
|
||||
chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
|
||||
chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
|
||||
|
||||
|
|
@ -2095,7 +2118,6 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
|
|||
|
||||
/* Enable Channel XORing for Dual Channel Interleave */
|
||||
if (sysinfo->interleaved) {
|
||||
|
||||
reg32 = MCHBAR32(DCC);
|
||||
reg32 &= ~(1 << 10);
|
||||
reg32 |= (1 << 9);
|
||||
|
|
@ -2193,16 +2215,20 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
#endif
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 667:
|
||||
MCHBAR32(HGIPMC2) = 0x0d590d59; break;
|
||||
MCHBAR32(HGIPMC2) = 0x0d590d59;
|
||||
break;
|
||||
case 533:
|
||||
MCHBAR32(HGIPMC2) = 0x155b155b; break;
|
||||
MCHBAR32(HGIPMC2) = 0x155b155b;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 667:
|
||||
MCHBAR32(HGIPMC2) = 0x09c409c4; break;
|
||||
MCHBAR32(HGIPMC2) = 0x09c409c4;
|
||||
break;
|
||||
case 533:
|
||||
MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
|
||||
MCHBAR32(HGIPMC2) = 0x0fa00fa0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2212,9 +2238,11 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
reg32 &= 0xffff0000;
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 667:
|
||||
reg32 |= 0x0600; break;
|
||||
reg32 |= 0x0600;
|
||||
break;
|
||||
case 533:
|
||||
reg32 |= 0x0480; break;
|
||||
reg32 |= 0x0480;
|
||||
break;
|
||||
}
|
||||
MCHBAR32(C2C3TT) = reg32;
|
||||
|
||||
|
|
@ -2222,9 +2250,11 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
reg32 &= 0xffff0000;
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 667:
|
||||
reg32 |= 0x0b80; break;
|
||||
reg32 |= 0x0b80;
|
||||
break;
|
||||
case 533:
|
||||
reg32 |= 0x0980; break;
|
||||
reg32 |= 0x0980;
|
||||
break;
|
||||
}
|
||||
MCHBAR32(C3C4TT) = reg32;
|
||||
|
||||
|
|
@ -2318,9 +2348,7 @@ static void sdram_thermal_management(void)
|
|||
MCHBAR8(TCO1) = 0x00;
|
||||
MCHBAR8(TCO0) = 0x00;
|
||||
|
||||
/* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
|
||||
* 0x30/0x32.
|
||||
*/
|
||||
/* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr 0x30/0x32. */
|
||||
|
||||
/* TODO This is not implemented yet. Volunteers? */
|
||||
}
|
||||
|
|
@ -2331,9 +2359,8 @@ static void sdram_save_receive_enable(void)
|
|||
u32 reg32;
|
||||
u8 values[4];
|
||||
|
||||
/* The following values are stored to an unused CMOS
|
||||
* area and restored instead of recalculated in case
|
||||
* of an S3 resume.
|
||||
/* The following values are stored to an unused CMOS area and restored instead of
|
||||
* recalculated in case of an S3 resume.
|
||||
*
|
||||
* C0WL0REOST [7:0] -> 8 bit
|
||||
* C1WL0REOST [7:0] -> 8 bit
|
||||
|
|
@ -2429,7 +2456,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo)
|
|||
MCHBAR32(ODTC) = reg32;
|
||||
|
||||
if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
|
||||
sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
|
||||
printk(BIOS_DEBUG, "one dimm per channel config..\n");
|
||||
|
||||
reg32 = MCHBAR32(C0ODT);
|
||||
|
|
@ -2485,10 +2512,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
|
|||
clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
|
||||
|
||||
#if CONFIG(OVERRIDE_CLOCK_DISABLE)
|
||||
/* Usually system firmware turns off system memory clock signals
|
||||
* to unused SO-DIMM slots to reduce EMI and power consumption.
|
||||
* However, the Kontron 986LCD-M does not like unused clock
|
||||
* signals to be disabled.
|
||||
/* Usually system firmware turns off system memory clock signals to unused SO-DIMM slots
|
||||
* to reduce EMI and power consumption.
|
||||
* However, the Kontron 986LCD-M does not like unused clock signals to be disabled.
|
||||
*/
|
||||
|
||||
clocks[0] = 0xf; /* force all clock gate pairs to enable */
|
||||
|
|
@ -2550,11 +2576,14 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
|
|||
/* Get CAS latency set up */
|
||||
switch (sysinfo->cas) {
|
||||
case 5:
|
||||
mrsaddr = MRS_CAS_5; break;
|
||||
mrsaddr = MRS_CAS_5;
|
||||
break;
|
||||
case 4:
|
||||
mrsaddr = MRS_CAS_4; break;
|
||||
mrsaddr = MRS_CAS_4;
|
||||
break;
|
||||
case 3:
|
||||
mrsaddr = MRS_CAS_3; break;
|
||||
mrsaddr = MRS_CAS_3;
|
||||
break;
|
||||
default:
|
||||
die("Jedec Error (CAS).\n");
|
||||
}
|
||||
|
|
@ -2562,11 +2591,14 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
|
|||
/* Get tWR set */
|
||||
switch (sysinfo->twr) {
|
||||
case 5:
|
||||
mrsaddr |= MRS_TWR_5; break;
|
||||
mrsaddr |= MRS_TWR_5;
|
||||
break;
|
||||
case 4:
|
||||
mrsaddr |= MRS_TWR_4; break;
|
||||
mrsaddr |= MRS_TWR_4;
|
||||
break;
|
||||
case 3:
|
||||
mrsaddr |= MRS_TWR_3; break;
|
||||
mrsaddr |= MRS_TWR_3;
|
||||
break;
|
||||
default:
|
||||
die("Jedec Error (tWR).\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -100,8 +100,7 @@ static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine)
|
|||
return -1;
|
||||
}
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2);
|
||||
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
|
||||
|
|
@ -123,8 +122,7 @@ static int find_preamble(int channel_offset, u8 *mediumcoarse,
|
|||
}
|
||||
*mediumcoarse -= 4;
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2);
|
||||
|
||||
reg32 = sample_strobes(channel_offset, sysinfo);
|
||||
|
||||
|
|
@ -155,8 +153,7 @@ static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine)
|
|||
return -1;
|
||||
}
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2);
|
||||
} else {
|
||||
*fine += 0x80;
|
||||
}
|
||||
|
|
@ -176,8 +173,7 @@ static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
|||
for (;;) {
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2);
|
||||
|
||||
rcvenmt = sample_strobes(channel_offset, sysinfo);
|
||||
|
||||
|
|
@ -210,8 +206,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
|||
printk(BIOS_SPEW, " %s()\n", __func__);
|
||||
|
||||
counter = 8;
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2);
|
||||
|
||||
for (;;) {
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
|
|
@ -249,8 +244,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
|||
*fine -= 7;
|
||||
if (*fine >= 0xf9) {
|
||||
*mediumcoarse -= 2;
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2);
|
||||
}
|
||||
|
||||
*fine &= ~(1 << 3);
|
||||
|
|
@ -265,8 +259,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
|||
* a lot of if ()s so let's just pass 0 or 0x80 for the channel offset.
|
||||
*/
|
||||
|
||||
static int receive_enable_autoconfig(int channel_offset,
|
||||
struct sys_info *sysinfo)
|
||||
static int receive_enable_autoconfig(int channel_offset, struct sys_info *sysinfo)
|
||||
{
|
||||
u8 mediumcoarse;
|
||||
u8 fine;
|
||||
|
|
|
|||
Loading…
Reference in New Issue