intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGE
Change-Id: Ie522e8fda1d6e80cc45c990ff19a5050165d8030 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -9,10 +9,6 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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ifneq ($(CONFIG_POSTCAR_STAGE),y)
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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else
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cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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endif
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romstage-y += ../car/romstage.c
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@ -23,6 +23,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select RELOCATABLE_RAMSTAGE
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select POSTCAR_STAGE
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config HW_SCRUBBER
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bool
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@ -6,4 +6,6 @@ ramstage-y += memmap.c
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romstage-y += raminit.c
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romstage-y += debug.c
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romstage-y += memmap.c
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postcar-y += memmap.c
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endif
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@ -37,9 +37,10 @@ void *cbmem_top(void)
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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/* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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void *setup_stack_and_mtrrs(void)
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/* platform_enter_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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@ -59,8 +60,7 @@ void *setup_stack_and_mtrrs(void)
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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/* Save the number of MTRRs to setup. Return the stack location
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* pointing to the number of MTRRs.
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*/
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return postcar_commit_mtrrs(&pcf);
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run_postcar_phase(&pcf);
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/* We do not return here. */
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}
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