coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz
Add ddr3-samsung-2GB config and modify 533mhz linit. Support ddr3 freq up to 800mhz. Enable ODT at LPDDR3. BUG=None TEST=Boot Veyron Pinky Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220113 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d (cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
jinkun.hong
Aaron Durbin
parent
bfdd732b80
commit
3e9ea16c54
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@ -28,7 +28,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
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#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
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@ -0,0 +1,78 @@
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{
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/* two Samsung K4B4G1646D-BYK0 chips */
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{
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{
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.rank = 0x1,
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.col = 0xA,
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.bk = 0x3,
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.bw = 0x2,
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.dbw = 0x1,
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.row_3_4 = 0x0,
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.cs0_row = 0xF,
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.cs1_row = 0xF
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},
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{
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.rank = 0x1,
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.col = 0xA,
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.bk = 0x3,
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.bw = 0x2,
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.dbw = 0x1,
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.row_3_4 = 0x0,
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.cs0_row = 0xF,
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.cs1_row = 0xF
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}
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},
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{
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.togcnt1u = 0x29A,
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.tinit = 0xC8,
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.trsth = 0x1F4,
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.togcnt100n = 0x42,
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.trefi = 0x4E,
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.tmrd = 0x4,
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.trfc = 0xEA,
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.trp = 0xA,
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.trtw = 0x5,
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.tal = 0x0,
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.tcl = 0xA,
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.tcwl = 0x7,
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.tras = 0x19,
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.trc = 0x24,
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.trcd = 0xA,
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.trrd = 0x7,
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.trtp = 0x5,
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.twr = 0xA,
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.twtr = 0x5,
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.texsr = 0x200,
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.txp = 0x5,
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.txpdll = 0x10,
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.tzqcs = 0x40,
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.tzqcsi = 0x0,
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.tdqs = 0x1,
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.tcksre = 0x7,
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.tcksrx = 0x7,
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.tcke = 0x4,
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.tmod = 0xC,
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.trstl = 0x43,
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.tzqcl = 0x100,
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.tmrr = 0x0,
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.tckesr = 0x5,
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.tdpd = 0x0
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},
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{
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.dtpr0 = 0x48F9AAB4,
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.dtpr1 = 0xEA0910,
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.dtpr2 = 0x1002C200,
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.mr[0] = 0xA60,
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.mr[1] = 0x40,
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.mr[2] = 0x10,
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.mr[3] = 0x0
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},
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.noc_timing = 0x30B25564,
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.noc_activate = 0x627,
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.ddrconfig = 3,
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.ddr_freq = 666000000,
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.dramtype = DDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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},
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@ -340,12 +340,12 @@ static struct rk3288_msch_regs * const rk3288_msch[2] = {
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#define PRT_DLLSRST(n) ((n) << 0)
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/* PTR1 */
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#define PRT_DINIT1(n) ((n) << 19)
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#define PRT_DINIT0(n) ((n) << 0)
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#define PRT_DINIT1(n) ((n) << 19)
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/* PTR2 */
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#define PRT_DINIT3(n) ((n) << 17)
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#define PRT_DINIT2(n) ((n) << 0)
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#define PRT_DINIT3(n) ((n) << 17)
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/* DCR */
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#define DDRMD_LPDDR 0
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@ -442,6 +442,7 @@ static struct rk3288_msch_regs * const rk3288_msch[2] = {
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#define DPDE_CMD (9)
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#define LPDDR2_MA(n) (((n) & 0xff) << 4)
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#define LPDDR2_OP(n) (((n) & 0xff) << 12)
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#define START_CMD (1u << 31)
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@ -620,7 +621,7 @@ static void pctl_cfg(u32 channel,
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writel(sdram_params->pctl_timing.tcwl - 1,
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&ddr_pctl_regs->dfitphywrlat);
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writel(MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN
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| DDR2_DDR3_BL_8 | TFAW_CFG(5) | PD_EXIT_SLOW
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| DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW
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| PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg);
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writel(MSCH_MAINDDR3(channel, 1), &rk3288_grf->soc_con0);
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@ -650,12 +651,19 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
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writel(sdram_params->noc_activate, &msch_regs->activate);
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writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1),
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&msch_regs->devtodev);
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writel(PRT_ITMSRST(8) | PRT_DLLLOCK(2750) | PRT_DLLSRST(27),
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&ddr_publ_regs->ptr[0]);
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/* tDINIT1=400ns (533MHz), tDINIT0=500us (533MHz) */
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writel(PRT_DINIT1(213) | PRT_DINIT0(266525), &ddr_publ_regs->ptr[1]);
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/* tDINIT3=1us (533MHz), tDINIT2=200us (533MHz) */
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writel(PRT_DINIT3(534) | PRT_DINIT2(106610), &ddr_publ_regs->ptr[2]);
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writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / 1000000
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* 5120, 1000))
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| PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / 1000000
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* 50, 1000))
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| PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]);
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writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq / 1000000
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* 500000, 1000))
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| PRT_DINIT1(div_round_up(sdram_params->ddr_freq / 1000000
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* 400, 1000)), &ddr_publ_regs->ptr[1]);
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writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq / 1000000
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* 200000, 1000))
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| PRT_DINIT3(div_round_up(sdram_params->ddr_freq / 1000000
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* 1000, 1000)), &ddr_publ_regs->ptr[2]);
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switch (sdram_params->dramtype) {
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case LPDDR3:
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@ -860,7 +868,7 @@ static int data_training(u32 channel,
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}
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}
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/* send some auto refresh to complement the lost while DTT */
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for (i = 0; i < (rank > 1 ? 4 : 2); i++)
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for (i = 0; i < (rank > 1 ? 8 : 4); i++)
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send_command(ddr_pctl_regs, rank, REF_CMD, 0);
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if (sdram_params->dramtype != LPDDR3)
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@ -962,7 +970,10 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
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int zqcr;
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printk(BIOS_INFO, "Starting SDRAM initialization...\n");
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if (sdram_params->ddr_freq > 533000000)
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if ((sdram_params->dramtype == DDR3
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&& sdram_params->ddr_freq > 800000000)
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|| (sdram_params->dramtype == LPDDR3
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&& sdram_params->ddr_freq > 533000000))
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die("SDRAM frequency is to high!");
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rkclk_configure_ddr(sdram_params->ddr_freq);
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@ -1011,6 +1022,10 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
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if (sdram_params->dramtype == LPDDR3) {
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/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
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udelay(10);
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send_command(ddr_pctl_regs,
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(sdram_params->ch[channel].rank | 1),
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MRS_CMD, LPDDR2_MA(11) |
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sdram_params->odt ? LPDDR2_OP(3) : 0);
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if (channel == 0) {
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writel(0, &ddr_pctl_regs->mrrcfg0);
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send_command(ddr_pctl_regs, 1, MRR_CMD,
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