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jinkun.hong 3e9ea16c54 coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz
Add ddr3-samsung-2GB config and modify 533mhz linit.
Support ddr3 freq up to 800mhz.
Enable ODT at LPDDR3.

BUG=None
TEST=Boot Veyron Pinky

Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220113
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>

Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d
(cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9239
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02 21:16:55 +02:00
3rdparty@2bc495fd31 3rdparty: Update submodule to get Tegra 132 binaries 2015-03-07 17:50:58 +01:00
documentation documentation: begin documenting our use of git submodules 2015-02-13 09:33:24 +01:00
payloads libpayload: usb: xhci: set ENT flag in last Normal TRB 2015-03-23 18:41:18 +01:00
src coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz 2015-04-02 21:16:55 +02:00
util cbfstool: add filetypes for FSP, MRC, SPC and MRC_CACHE 2015-03-30 21:45:11 +02:00
.gitignore .gitignore: add the doxygen directory. 2014-12-14 23:30:45 +01:00
.gitmodules nvidia/cbootimage: avoid upstream's build system 2014-10-02 10:26:58 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile build system: generalize src-to-obj 2015-03-30 20:41:17 +02:00
Makefile.inc build system: make CONFIG_* symbols disappear from objects 2015-04-01 00:29:18 +02:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc mips: mips, not mipsel 2015-03-29 22:38:57 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.