Drop southbridge intel/i82801cx
All boards using this southbridge have been removed from the tree already. Change-Id: I08269931d845d1f57b34174238bcce245ad77894 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12237 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
parent
31ff120a2c
commit
3efcd2eeee
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@ -1,4 +0,0 @@
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config SOUTHBRIDGE_INTEL_I82801CX
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bool
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select IOAPIC
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select HAVE_HARD_RESET
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@ -1,12 +0,0 @@
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801CX),y)
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ramstage-y += i82801cx.c
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ramstage-y += usb.c
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ramstage-y += lpc.c
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ramstage-y += ide.c
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ramstage-y += ac97.c
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#ramstage-y += nic.c
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ramstage-y += pci.c
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ramstage-y += reset.c
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endif
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@ -1,41 +0,0 @@
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/*
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* (C) 2003 Linux Networx
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "i82801cx.h"
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static struct device_operations ac97audio_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = i82801cx_enable,
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.init = 0,
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.scan_bus = 0,
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};
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static const struct pci_driver ac97audio_driver __pci_driver = {
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.ops = &ac97audio_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO,
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};
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static struct device_operations ac97modem_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = i82801cx_enable,
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.init = 0,
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.scan_bus = 0,
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};
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static const struct pci_driver ac97modem_driver __pci_driver = {
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.ops = &ac97modem_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM,
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};
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@ -1,134 +0,0 @@
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#include <device/pci_ids.h>
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#include "i82801cx.h"
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static void enable_smbus(void)
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{
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device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
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printk(BIOS_DEBUG, "SMBus controller enabled\n");
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/* set smbus iobase */
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pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
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/* Set smbus enable */
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pci_write_config8(dev, HOSTC, HST_EN);
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/* Set smbus iospace enable */
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
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/* Disable interrupt generation */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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}
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static inline void smbus_delay(void)
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{
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outb(0x80, 0x80);
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}
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// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html
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// for a description of this function.
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static int smbus_wait_until_active(void)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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if ((val & 1)) {
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break;
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}
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} while (--loops);
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return loops ? 0 : -4;
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}
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static int smbus_wait_until_ready(void)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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// !HOST_BUSY?
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if ((val & 1) == 0) {
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break;
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}
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if(loops == (SMBUS_TIMEOUT / 2)) {
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// Clear status flags
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
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SMBUS_IO_BASE + SMBHSTSTAT);
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}
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} while(--loops);
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return loops?0:-2;
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}
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static int smbus_wait_until_done(void)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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// !HOST_BUSY?
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if ( (val & 1) == 0) {
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break;
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}
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// BYTE_DONE or SUCCESS or error?
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if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
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break;
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}
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} while(--loops);
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return loops?0:-3;
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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unsigned char global_control_register;
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready() < 0) {
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return -2;
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}
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/* setup transaction */
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/* disable interrupts */
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outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
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/* set to read from the specified device */
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outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
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/* set the command/address... */
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set up for a byte data read */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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/* clear the data byte...*/
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outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
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/* start a byte read, with interrupts disabled */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
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/* poll for it to start */
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if (smbus_wait_until_active() < 0) {
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return -4;
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}
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/* poll for transaction completion */
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if (smbus_wait_until_done() < 0) {
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return -3;
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}
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global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
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/* read results of transaction */
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byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
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// SUCCESS?
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if (global_status_register != 2) {
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return -1;
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}
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return byte;
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}
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <assert.h>
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#include "i82801cx.h"
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void i82801cx_enable(device_t dev)
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{
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unsigned int index = 0;
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uint8_t bHasDisableBit = 0;
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uint16_t cur_disable_mask, new_disable_mask;
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// all 82801ca devices are in bus 0
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unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
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device_t lpc_dev = dev_find_slot(0, devfn); // 0
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if (!lpc_dev)
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return;
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// Calculate disable bit position for specified device:function
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// NOTE: For ICH-3, only the following devices can be disabled:
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// D31:F1, D31:F3, D31:F5, D31:F6,
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// D29:F0, D29:F1, D29:F2
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if (PCI_SLOT(dev->path.pci.devfn) == 31) {
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index = PCI_FUNC(dev->path.pci.devfn);
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if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
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bHasDisableBit = 1;
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} else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
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index = 8 + PCI_FUNC(dev->path.pci.devfn);
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if (PCI_FUNC(dev->path.pci.devfn) < 3)
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bHasDisableBit = 1;
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}
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if (bHasDisableBit) {
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cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
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new_disable_mask = cur_disable_mask & ~(1<<index); // enable it
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if (!dev->enabled) {
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new_disable_mask |= (1<<index); // disable it
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}
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if (new_disable_mask != cur_disable_mask) {
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pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
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}
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}
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}
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struct chip_operations southbridge_intel_i82801cx_ops = {
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CHIP_NAME("Intel ICH3 (82801Cx) Series Southbridge")
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.enable_dev = i82801cx_enable,
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};
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#ifndef I82801CX_H
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#define I82801CX_H
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#if !defined(__PRE_RAM__)
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#include <device/device.h>
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void i82801cx_enable(device_t dev);
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#endif
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#define PCI_DMA_CFG 0x90
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#define SERIRQ_CNTL 0x64
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#define GEN_CNTL 0xd0
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#define GEN_STS 0xd4
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#define RTC_CONF 0xd8
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#define GEN_PMCON_3 0xa4
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE 0x58
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#define GPIO_CNTL 0x5C
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#define PIRQA_ROUT 0x60
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#define PIRQE_ROUT 0x68
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#define COM_DEC 0xE0
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#define LPC_EN 0xE6
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#define FUNC_DIS 0xF2
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// GEN_PMCON_3 bits
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#define RTC_BATTERY_DEAD (1<<2)
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#define RTC_POWER_FAILED (1<<1)
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#define SLEEP_AFTER_POWER_FAIL (1<<0)
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/* IDE controller: */
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// PCI Configuration Space (D31:F1)
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#define IDE_TIM_PRI 0x40 // IDE timings, primary
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#define IDE_TIM_SEC 0x42 // IDE timings, secondary
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// IDE_TIM bits
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#define IDE_DECODE_ENABLE (1<<15)
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/* SMBus: */
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// PCI Configuration Space (D31:F3)
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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// HOSTC bits
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#define I2C_EN (1<<2)
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#define SMB_SMI_EN (1<<1)
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#define HST_EN (1<<0)
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#define SMBUS_IO_BASE 0x1000
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// I/O registers (relative to SMBUS_IO_BASE)
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#define SMBHSTSTAT 0
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#define SMBHSTCTL 2
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#define SMBHSTCMD 3
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#define SMBXMITADD 4
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#define SMBHSTDAT0 5
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#define SMBHSTDAT1 6
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#define SMBBLKDAT 7
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#define SMBTRNSADD 9
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#define SMBSLVDATA 10
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#define SMLINK_PIN_CTL 14
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#define SMBUS_PIN_CTL 15
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/* Between 1-10 seconds, We should never timeout normally
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* Longer than this is just painful when a timeout condition occurs.
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*/
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#define SMBUS_TIMEOUT (100*1000)
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#endif /* I82801CX_H */
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@ -1,48 +0,0 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "i82801cx.h"
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static void ide_init(struct device *dev)
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{
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/* Enable ide devices so the linux ide driver will work */
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uint16_t ideTimingConfig;
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int enable_primary = 1;
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int enable_secondary = 1;
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (enable_primary) {
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/* Enable first ide interface */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE0 ");
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}
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pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (enable_secondary) {
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/* Enable secondary ide interface */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE1 ");
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}
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pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.scan_bus = 0,
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.enable = i82801cx_enable,
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};
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static const struct pci_driver ide_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801CA_IDE,
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};
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@ -1,241 +0,0 @@
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/*
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* (C) 2003 Linux Networx, SuSE Linux AG
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* (C) 2004 Tyan Computer
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|
||||||
* (c) 2005 Digital Design Corporation
|
|
||||||
*/
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include <pc80/mc146818rtc.h>
|
|
||||||
#include <pc80/isa-dma.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include <arch/ioapic.h>
|
|
||||||
#include "i82801cx.h"
|
|
||||||
|
|
||||||
#define NMI_OFF 0
|
|
||||||
|
|
||||||
#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
|
||||||
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define MAINBOARD_POWER_OFF 0
|
|
||||||
#define MAINBOARD_POWER_ON 1
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Set miscellanous static southbridge features.
|
|
||||||
*
|
|
||||||
* @param dev PCI device with I/O APIC control registers
|
|
||||||
*/
|
|
||||||
static void i82801cx_enable_ioapic(struct device *dev)
|
|
||||||
{
|
|
||||||
u32 reg32;
|
|
||||||
|
|
||||||
reg32 = pci_read_config32(dev, GEN_CNTL);
|
|
||||||
reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
|
|
||||||
reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
|
|
||||||
reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
|
|
||||||
reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
|
|
||||||
pci_write_config32(dev, GEN_CNTL, reg32);
|
|
||||||
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
|
|
||||||
|
|
||||||
set_ioapic_id(VIO_APIC_VADDR, 0x02);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Select Boot Configuration register (0x03) and
|
|
||||||
* use Processor System Bus (0x01) to deliver interrupts.
|
|
||||||
*/
|
|
||||||
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
|
|
||||||
}
|
|
||||||
|
|
||||||
// This is how interrupts are received from the Super I/O chip
|
|
||||||
static void i82801cx_enable_serial_irqs( struct device *dev)
|
|
||||||
{
|
|
||||||
// Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
|
|
||||||
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Route all DMA channels to either PCI or LPC.
|
|
||||||
*
|
|
||||||
* @param dev TODO
|
|
||||||
* @param mask Identifies whether each channel should be used for PCI DMA
|
|
||||||
* (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
|
|
||||||
* Channel 4 is not used (reserved).
|
|
||||||
*/
|
|
||||||
static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
|
|
||||||
{
|
|
||||||
uint16_t dmaConfig;
|
|
||||||
int channelIndex;
|
|
||||||
|
|
||||||
dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
|
|
||||||
dmaConfig &= 0x300; // Preserve reserved bits
|
|
||||||
for(channelIndex = 0; channelIndex < 8; channelIndex++) {
|
|
||||||
if (channelIndex == 4)
|
|
||||||
continue; // Register doesn't support channel 4
|
|
||||||
dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2);
|
|
||||||
}
|
|
||||||
pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void i82801cx_rtc_init(struct device *dev)
|
|
||||||
{
|
|
||||||
uint32_t dword;
|
|
||||||
int rtc_failed;
|
|
||||||
int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
|
||||||
uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
|
|
||||||
|
|
||||||
rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
|
|
||||||
if (rtc_failed) {
|
|
||||||
// Clear the RTC_BATTERY_DEAD bit, but preserve
|
|
||||||
// the RTC_POWER_FAILED, G3 state, and reserved bits
|
|
||||||
// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
|
|
||||||
pmcon3 &= ~RTC_POWER_FAILED;
|
|
||||||
}
|
|
||||||
|
|
||||||
get_option(&pwr_on, "power_on_after_fail");
|
|
||||||
pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
|
|
||||||
if (!pwr_on) {
|
|
||||||
pmcon3 |= SLEEP_AFTER_POWER_FAIL;
|
|
||||||
}
|
|
||||||
pci_write_config8(dev, GEN_PMCON_3, pmcon3);
|
|
||||||
printk(BIOS_INFO, "set power %s after power fail\n",
|
|
||||||
pwr_on ? "on" : "off");
|
|
||||||
|
|
||||||
// See if the Safe Mode jumper is set
|
|
||||||
dword = pci_read_config32(dev, GEN_STS);
|
|
||||||
rtc_failed |= dword & (1 << 2);
|
|
||||||
|
|
||||||
cmos_init(rtc_failed);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static void i82801cx_1f0_misc(struct device *dev)
|
|
||||||
{
|
|
||||||
// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
|
|
||||||
pci_write_config16(dev, PCI_COMMAND, 0x014f);
|
|
||||||
|
|
||||||
// Set ACPI base address to 0x1100 (I/O space)
|
|
||||||
pci_write_config32(dev, PMBASE, 0x00001101);
|
|
||||||
|
|
||||||
// Enable ACPI I/O and power management
|
|
||||||
pci_write_config8(dev, ACPI_CNTL, 0x10);
|
|
||||||
|
|
||||||
// Set GPIO base address to 0x1180 (I/O space)
|
|
||||||
pci_write_config32(dev, GPIO_BASE, 0x00001181);
|
|
||||||
|
|
||||||
// Enable GPIO
|
|
||||||
pci_write_config8(dev, GPIO_CNTL, 0x10);
|
|
||||||
|
|
||||||
// Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10
|
|
||||||
pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
|
|
||||||
|
|
||||||
// Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted.
|
|
||||||
pci_write_config8(dev, PIRQE_ROUT, 0x07);
|
|
||||||
|
|
||||||
// Enable access to the upper 128 byte bank of CMOS RAM
|
|
||||||
pci_write_config8(dev, RTC_CONF, 0x04);
|
|
||||||
|
|
||||||
// Decode 0x3F8-0x3FF (COM1) for COMA port,
|
|
||||||
// 0x2F8-0x2FF (COM2) for COMB
|
|
||||||
pci_write_config8(dev, COM_DEC, 0x10);
|
|
||||||
|
|
||||||
// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
|
|
||||||
// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
|
|
||||||
|
|
||||||
// Enable COMA, COMB, LPT, floppy;
|
|
||||||
// disable microcontroller, Super I/O, sound, gameport
|
|
||||||
pci_write_config16(dev, LPC_EN, 0x000F);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void lpc_init(struct device *dev)
|
|
||||||
{
|
|
||||||
uint8_t byte;
|
|
||||||
int pwr_on=-1;
|
|
||||||
int nmi_option;
|
|
||||||
|
|
||||||
/* IO APIC initialization */
|
|
||||||
i82801cx_enable_ioapic(dev);
|
|
||||||
|
|
||||||
i82801cx_enable_serial_irqs(dev);
|
|
||||||
|
|
||||||
/* power after power fail */
|
|
||||||
/* FIXME this doesn't work! */
|
|
||||||
/* Which state do we want to goto after g3 (power restored)?
|
|
||||||
* 0 == S0 Full On
|
|
||||||
* 1 == S5 Soft Off
|
|
||||||
*/
|
|
||||||
byte = pci_read_config8(dev, GEN_PMCON_3);
|
|
||||||
if (pwr_on)
|
|
||||||
byte &= ~1; // Return to S0 (boot) after power is re-applied
|
|
||||||
else
|
|
||||||
byte |= 1; // Return to S5
|
|
||||||
pci_write_config8(dev, GEN_PMCON_3, byte);
|
|
||||||
printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
|
|
||||||
|
|
||||||
/* Set up NMI on errors */
|
|
||||||
byte = inb(0x61);
|
|
||||||
byte &= ~(1 << 3); /* IOCHK# NMI Enable */
|
|
||||||
byte &= ~(1 << 2); /* PCI SERR# Enable */
|
|
||||||
outb(byte, 0x61);
|
|
||||||
byte = inb(0x70);
|
|
||||||
nmi_option = NMI_OFF;
|
|
||||||
get_option(&nmi_option, "nmi");
|
|
||||||
if (nmi_option) {
|
|
||||||
byte &= ~(1 << 7); /* set NMI */
|
|
||||||
outb(byte, 0x70);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Initialize the real time clock */
|
|
||||||
i82801cx_rtc_init(dev);
|
|
||||||
|
|
||||||
i82801cx_lpc_route_dma(dev, 0xff);
|
|
||||||
|
|
||||||
/* Initialize isa dma */
|
|
||||||
isa_dma_init();
|
|
||||||
|
|
||||||
i82801cx_1f0_misc(dev);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void i82801cx_lpc_read_resources(device_t dev)
|
|
||||||
{
|
|
||||||
struct resource *res;
|
|
||||||
|
|
||||||
/* Get the normal PCI resources of this device. */
|
|
||||||
pci_dev_read_resources(dev);
|
|
||||||
|
|
||||||
/* Add an extra subtractive resource for both memory and I/O. */
|
|
||||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
|
||||||
res->base = 0;
|
|
||||||
res->size = 0x1000;
|
|
||||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
|
||||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
||||||
|
|
||||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
|
||||||
res->base = 0xff800000;
|
|
||||||
res->size = 0x00800000; /* 8 MB for flash */
|
|
||||||
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
|
||||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
||||||
|
|
||||||
res = new_resource(dev, 3); /* IOAPIC */
|
|
||||||
res->base = IO_APIC_ADDR;
|
|
||||||
res->size = 0x00001000;
|
|
||||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct device_operations lpc_ops = {
|
|
||||||
.read_resources = i82801cx_lpc_read_resources,
|
|
||||||
.set_resources = pci_dev_set_resources,
|
|
||||||
.enable_resources = pci_dev_enable_resources,
|
|
||||||
.init = lpc_init,
|
|
||||||
.scan_bus = scan_lpc_bus,
|
|
||||||
.enable = 0,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct pci_driver lpc_driver __pci_driver = {
|
|
||||||
.ops = &lpc_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_INTEL,
|
|
||||||
.device = PCI_DEVICE_ID_INTEL_82801CA_LPC,
|
|
||||||
};
|
|
||||||
|
|
@ -1,21 +0,0 @@
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include "i82801cx.h"
|
|
||||||
|
|
||||||
|
|
||||||
static struct device_operations nic_ops = {
|
|
||||||
.read_resources = pci_dev_read_resources,
|
|
||||||
.set_resources = pci_dev_set_resources,
|
|
||||||
.enable_resources = pci_dev_enable_resources,
|
|
||||||
.init = 0,
|
|
||||||
.scan_bus = 0,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct pci_driver nic_driver __pci_driver = {
|
|
||||||
.ops = &nic_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_INTEL,
|
|
||||||
.device = PCI_DEVICE_ID_INTEL_82801CA_LAN,
|
|
||||||
};
|
|
||||||
|
|
@ -1,29 +0,0 @@
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include "i82801cx.h"
|
|
||||||
|
|
||||||
static void pci_init(struct device *dev)
|
|
||||||
{
|
|
||||||
// NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F)
|
|
||||||
/* Enable pci error detecting */
|
|
||||||
uint32_t dword = pci_read_config32(dev, PCI_COMMAND);
|
|
||||||
dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
|
|
||||||
pci_write_config32(dev, PCI_COMMAND, dword);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct device_operations pci_ops = {
|
|
||||||
.read_resources = pci_bus_read_resources,
|
|
||||||
.set_resources = pci_dev_set_resources,
|
|
||||||
.enable_resources = pci_bus_enable_resources,
|
|
||||||
.init = pci_init,
|
|
||||||
.scan_bus = pci_scan_bridge,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct pci_driver pci_driver __pci_driver = {
|
|
||||||
.ops = &pci_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_INTEL,
|
|
||||||
.device = PCI_DEVICE_ID_INTEL_82801CA_PCI,
|
|
||||||
};
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
#include <arch/io.h>
|
|
||||||
#include <reset.h>
|
|
||||||
|
|
||||||
void hard_reset(void)
|
|
||||||
{
|
|
||||||
/* Try rebooting through port 0xcf9 */
|
|
||||||
// Hard reset without power cycle
|
|
||||||
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
|
|
||||||
}
|
|
||||||
|
|
@ -1,83 +0,0 @@
|
||||||
#include <smbus.h>
|
|
||||||
#include <pci.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include "i82801cx.h"
|
|
||||||
|
|
||||||
#define PM_BUS 0
|
|
||||||
#define PM_DEVFN PCI_DEVFN(0x1f,3)
|
|
||||||
|
|
||||||
void smbus_enable(void)
|
|
||||||
{
|
|
||||||
/* iobase addr */
|
|
||||||
pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE,
|
|
||||||
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
|
|
||||||
/* smbus enable */
|
|
||||||
pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);
|
|
||||||
/* iospace enable */
|
|
||||||
pcibios_write_config_word(PM_BUS, PM_DEVFN, PCI_COMMAND, PCI_COMMAND_IO);
|
|
||||||
|
|
||||||
/* Disable interrupt generation */
|
|
||||||
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void smbus_wait_until_ready(void)
|
|
||||||
{
|
|
||||||
// Loop while HOST_BUSY
|
|
||||||
while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
|
|
||||||
/* nop */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void smbus_wait_until_done(void)
|
|
||||||
{
|
|
||||||
unsigned char byte;
|
|
||||||
|
|
||||||
// Loop while HOST_BUSY
|
|
||||||
do {
|
|
||||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
|
||||||
}
|
|
||||||
while((byte &1) == 1);
|
|
||||||
|
|
||||||
// Wait for SUCCESS or error or BYTE_DONE
|
|
||||||
while( (byte & ~1) == 0) {
|
|
||||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
|
|
||||||
{
|
|
||||||
unsigned char host_status_register;
|
|
||||||
unsigned char byte;
|
|
||||||
|
|
||||||
smbus_wait_until_ready();
|
|
||||||
|
|
||||||
/* setup transaction */
|
|
||||||
/* disable interrupts */
|
|
||||||
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
|
|
||||||
/* set to read from the specified device */
|
|
||||||
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
|
|
||||||
/* set the command/address... */
|
|
||||||
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
|
|
||||||
/* set up for a byte data read */
|
|
||||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
|
|
||||||
|
|
||||||
/* clear any lingering errors, so the transaction will run */
|
|
||||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
|
||||||
|
|
||||||
/* clear the data byte...*/
|
|
||||||
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
|
|
||||||
|
|
||||||
/* start the command */
|
|
||||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
|
|
||||||
|
|
||||||
/* poll for transaction completion */
|
|
||||||
smbus_wait_until_done();
|
|
||||||
|
|
||||||
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
|
||||||
|
|
||||||
/* read results of transaction */
|
|
||||||
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
|
|
||||||
|
|
||||||
*result = byte;
|
|
||||||
return host_status_register != 0x02; // return true if !SUCCESS
|
|
||||||
}
|
|
||||||
|
|
@ -1,48 +0,0 @@
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include "i82801cx.h"
|
|
||||||
|
|
||||||
static void usb_init(struct device *dev)
|
|
||||||
{
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
uint32_t cmd;
|
|
||||||
printk(BIOS_DEBUG, "USB: Setting up controller.. ");
|
|
||||||
cmd = pci_read_config32(dev, PCI_COMMAND);
|
|
||||||
pci_write_config32(dev, PCI_COMMAND,
|
|
||||||
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
|
||||||
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
|
|
||||||
|
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "done.\n");
|
|
||||||
#endif
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct device_operations usb_ops = {
|
|
||||||
.read_resources = pci_dev_read_resources,
|
|
||||||
.set_resources = pci_dev_set_resources,
|
|
||||||
.enable_resources = pci_dev_enable_resources,
|
|
||||||
.init = usb_init,
|
|
||||||
.scan_bus = 0,
|
|
||||||
.enable = i82801cx_enable,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct pci_driver usb_driver_1 __pci_driver = {
|
|
||||||
.ops = &usb_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_INTEL,
|
|
||||||
.device = PCI_DEVICE_ID_INTEL_82801CA_USB1,
|
|
||||||
};
|
|
||||||
static const struct pci_driver usb_driver_2 __pci_driver = {
|
|
||||||
.ops = &usb_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_INTEL,
|
|
||||||
.device = PCI_DEVICE_ID_INTEL_82801CA_USB2,
|
|
||||||
};
|
|
||||||
static const struct pci_driver usb_driver_3 __pci_driver = {
|
|
||||||
.ops = &usb_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_INTEL,
|
|
||||||
.device = PCI_DEVICE_ID_INTEL_82801CA_USB3,
|
|
||||||
};
|
|
||||||
Loading…
Reference in New Issue