southbridge/intel/i82801gx: Fix problems found by checkpatch.pl
Change-Id: Iddc67e7c126ce19429afc24b021e385353564cb8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18705 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
70a8e34853
commit
3f111b0b11
16 changed files with 323 additions and 197 deletions
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@ -96,9 +96,8 @@ static int ac97_semaphore(void)
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reg8 = inb(nabmbar + CAS);
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timeout--;
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} while ((reg8 & 1) && timeout);
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if (! timeout) {
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if (!timeout)
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printk(BIOS_DEBUG, "Timeout!\n");
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}
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return (!timeout);
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}
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@ -220,7 +219,7 @@ static void ac97_modem_init(struct device *dev)
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mbar = pci_read_config16(dev, MBAR) & 0xfffe;
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reg16 = inw(mmbar + EXT_MODEM_ID1);
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if ((reg16 & 0xc000) != 0xc000 ) {
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if ((reg16 & 0xc000) != 0xc000) {
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if (reg16 & (1 << 0)) {
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reg32 = inw(mmbar + VENDOR_ID2);
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reg32 <<= 16;
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@ -247,7 +246,8 @@ static void ac97_modem_init(struct device *dev)
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}
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}
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static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void ac97_set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -87,9 +87,9 @@ no_codec:
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return 0;
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}
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static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
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static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb)
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{
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int idx=0;
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int idx = 0;
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while (idx < (cim_verb_data_size / sizeof(u32))) {
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u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
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@ -303,7 +303,8 @@ static void azalia_init(struct device *dev)
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}
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}
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static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void azalia_set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -38,15 +38,15 @@ int southbridge_detect_s3_resume(void)
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reg32 = inl(DEFAULT_PMBASE + 0x04);
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printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
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if (((reg32 >> 10) & 7) == 5) {
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if (acpi_s3_resume_allowed()) {
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if (!acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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} else {
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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/* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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return 1;
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} else {
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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}
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}
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@ -29,9 +29,8 @@ void enable_smbus(void)
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dev = PCI_DEV(0x0, 0x1f, 0x3);
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/* Check to make sure we've got the right device. */
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if (pci_read_config16(dev, 0x2) != 0x27da) {
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if (pci_read_config16(dev, 0x2) != 0x27da)
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die("SMBus controller not found!");
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}
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/* Set SMBus I/O base. */
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pci_write_config32(dev, SMB_BASE,
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@ -51,7 +50,7 @@ void enable_smbus(void)
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printk(BIOS_DEBUG, "SMBus controller enabled.\n");
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}
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int smbus_read_byte(unsigned device, unsigned address)
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int smbus_read_byte(unsigned int device, unsigned int address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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@ -49,7 +49,7 @@ void i82801gx_enable(device_t dev);
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void gpi_route_interrupt(u8 gpi, u8 mode);
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#else
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void enable_smbus(void);
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int smbus_read_byte(unsigned device, unsigned address);
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int smbus_read_byte(unsigned int device, unsigned int address);
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int southbridge_detect_s3_resume(void);
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#endif
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#endif
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@ -200,9 +200,9 @@ int southbridge_detect_s3_resume(void);
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/* Root Complex Register Block */
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#define RCBA 0xf0
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#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
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#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
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#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
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#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x))))
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#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))
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#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x))))
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#define VCH 0x0000 /* 32bit */
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#define VCAP1 0x0004 /* 32bit */
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@ -295,9 +295,9 @@ int southbridge_detect_s3_resume(void);
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* If UHCI controllers get disabled, EHCI
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* must know about it, too! */
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#define FD_UHCI4 (1 << 11)
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#define FD_UHCI34 (1 << 10) | FD_UHCI4
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#define FD_UHCI234 (1 << 9) | FD_UHCI3
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#define FD_UHCI1234 (1 << 8) | FD_UHCI2
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#define FD_UHCI34 ((1 << 10) | FD_UHCI4)
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#define FD_UHCI234 ((1 << 9) | FD_UHCI3)
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#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)
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#define FD_INTLAN (1 << 7)
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#define FD_ACMOD (1 << 6)
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@ -91,7 +91,8 @@ static void ide_init(struct device *dev)
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printk(BIOS_DEBUG, "\n");
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}
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static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void ide_set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -109,7 +109,7 @@ static void i82801gx_pirq_init(device_t dev)
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*/
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for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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u8 int_pin=0, int_line=0;
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u8 int_pin = 0, int_line = 0;
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if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
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continue;
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@ -117,10 +117,14 @@ static void i82801gx_pirq_init(device_t dev)
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int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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switch (int_pin) {
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case 1: /* INTA# */ int_line = config->pirqa_routing; break;
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case 2: /* INTB# */ int_line = config->pirqb_routing; break;
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case 3: /* INTC# */ int_line = config->pirqc_routing; break;
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case 4: /* INTD# */ int_line = config->pirqd_routing; break;
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case 1:
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/* INTA# */ int_line = config->pirqa_routing; break;
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case 2:
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/* INTB# */ int_line = config->pirqb_routing; break;
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case 3:
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/* INTC# */ int_line = config->pirqc_routing; break;
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case 4:
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/* INTD# */ int_line = config->pirqd_routing; break;
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}
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if (!int_line)
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@ -168,7 +172,7 @@ static void i82801gx_power_options(device_t dev)
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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int nmi_option;
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/* Which state do we want to goto after g3 (power restored)?
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@ -221,7 +225,7 @@ static void i82801gx_power_options(device_t dev)
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reg8 &= ~(1 << 7); /* Set NMI. */
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} else {
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printk(BIOS_INFO, "NMI sources disabled.\n");
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reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
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reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
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}
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outb(reg8, 0x70);
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@ -321,7 +325,7 @@ static void enable_clock_gating(void)
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reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
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reg32 |= (1 << 2); // PCIe clock gating;
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reg32 &= ~(1 << 20); // No static clock gating for USB
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reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
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reg32 &= ~((1 << 29) | (1 << 28)); // Disable UHCI clock gating
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RCBA32(CG) = reg32;
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}
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@ -481,9 +485,9 @@ unsigned long acpi_fill_madt(unsigned long current)
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return current;
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}
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void acpi_fill_fadt(acpi_fadt_t * fadt)
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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config_t *chip = dev->chip_info;
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u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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@ -586,19 +590,17 @@ void acpi_fill_fadt(acpi_fadt_t * fadt)
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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if (chip->p_cnt_throttling_supported) {
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if (chip->p_cnt_throttling_supported)
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fadt->duty_width = 3;
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} else {
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else
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fadt->duty_width = 0;
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}
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fadt->iapc_boot_arch = 0x03;
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fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
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| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
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| ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
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| ACPI_FADT_C2_MP_SUPPORTED);
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if (chip->docking_supported) {
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if (chip->docking_supported)
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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}
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}
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static void i82801gx_lpc_read_resources(device_t dev)
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@ -643,7 +645,8 @@ static void i82801gx_lpc_read_resources(device_t dev)
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}
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}
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static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -656,7 +659,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void southbridge_inject_dsdt(device_t dev)
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{
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global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
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global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
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if (gnvs) {
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const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
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@ -106,7 +106,8 @@ static void ich_pci_bus_enable_resources(struct device *dev)
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ich_pci_dev_enable_resources(dev);
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}
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static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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@ -89,7 +89,8 @@ static void pci_init(struct device *dev)
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pci_write_config16(dev, 0x1e, reg16);
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}
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static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void pcie_set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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@ -125,7 +126,7 @@ static const unsigned short i82801gx_pcie_ids[] = {
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};
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static const struct pci_driver i82801gx_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices= i82801gx_pcie_ids,
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = i82801gx_pcie_ids,
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};
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@ -199,7 +199,8 @@ static void sata_init(struct device *dev)
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pci_write_config32(dev, SATA_IR, reg32);
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}
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static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void sata_set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -236,7 +237,7 @@ static const unsigned short sata_ids[] = {
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};
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static const struct pci_driver i82801gx_sata_driver __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices= sata_ids,
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = sata_ids,
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};
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@ -38,7 +38,8 @@ static int lsmbus_read_byte(device_t dev, u8 address)
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return do_smbus_read_byte(res->base, device, address);
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}
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static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
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static int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
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unsigned int address, unsigned int data)
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{
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unsigned char global_status_register;
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@ -92,8 +93,8 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
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return do_smbus_write_byte(res->base, device, address, data);
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}
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static int do_smbus_block_write(unsigned smbus_base, unsigned device,
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unsigned cmd, unsigned bytes, const u8 *buf)
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static int do_smbus_block_write(unsigned int smbus_base, unsigned int device,
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unsigned int cmd, unsigned int bytes, const u8 *buf)
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{
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u8 status;
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@ -123,7 +124,8 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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while (!(inb(smbus_base + SMBHSTSTAT) & 1));
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while (!(inb(smbus_base + SMBHSTSTAT) & 1))
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;
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/* Poll for transaction completion */
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do {
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status = inb(smbus_base + SMBHSTSTAT);
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@ -155,8 +157,8 @@ static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
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return do_smbus_block_write(res->base, device, cmd, bytes, buf);
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}
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static int do_smbus_block_read(unsigned smbus_base, unsigned device,
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unsigned cmd, unsigned bytes, u8 *buf)
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static int do_smbus_block_read(unsigned int smbus_base, unsigned int device,
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unsigned int cmd, unsigned int bytes, u8 *buf)
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{
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u8 status;
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int bytes_read = 0;
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@ -180,7 +182,8 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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while (!(inb(smbus_base + SMBHSTSTAT) & 1));
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while (!(inb(smbus_base + SMBHSTSTAT) & 1))
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;
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/* Poll for transaction completion */
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do {
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status = inb(smbus_base + SMBHSTSTAT);
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@ -225,7 +228,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
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.block_write = lsmbus_block_write,
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};
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static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void smbus_set_subsystem(device_t dev, unsigned int vendor, unsigned int device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -24,7 +24,7 @@ static void smbus_delay(void)
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static int smbus_wait_until_ready(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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@ -37,7 +37,7 @@ static int smbus_wait_until_ready(u16 smbus_base)
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static int smbus_wait_until_done(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
|
||||
unsigned int loops = SMBUS_TIMEOUT;
|
||||
unsigned char byte;
|
||||
do {
|
||||
smbus_delay();
|
||||
|
|
@ -48,14 +48,13 @@ static int smbus_wait_until_done(u16 smbus_base)
|
|||
return loops ? 0 : -1;
|
||||
}
|
||||
|
||||
static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
|
||||
static int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, unsigned int address)
|
||||
{
|
||||
unsigned char global_status_register;
|
||||
unsigned char byte;
|
||||
|
||||
if (smbus_wait_until_ready(smbus_base) < 0) {
|
||||
if (smbus_wait_until_ready(smbus_base) < 0)
|
||||
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
}
|
||||
/* Setup transaction */
|
||||
/* Disable interrupts */
|
||||
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
|
||||
|
|
@ -77,9 +76,8 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add
|
|||
smbus_base + SMBHSTCTL);
|
||||
|
||||
/* Poll for transaction completion */
|
||||
if (smbus_wait_until_done(smbus_base) < 0) {
|
||||
if (smbus_wait_until_done(smbus_base) < 0)
|
||||
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
|
||||
}
|
||||
|
||||
global_status_register = inb(smbus_base + SMBHSTSTAT);
|
||||
|
||||
|
|
@ -88,8 +86,7 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add
|
|||
|
||||
/* Read results of transaction */
|
||||
byte = inb(smbus_base + SMBHSTDAT0);
|
||||
if (global_status_register != (1 << 1)) {
|
||||
if (global_status_register != (1 << 1))
|
||||
return SMBUS_ERROR;
|
||||
}
|
||||
return byte;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -57,14 +57,22 @@ static u16 reset_pm1_status(void)
|
|||
static void dump_pm1_status(u16 pm1_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "PM1_STS: ");
|
||||
if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
|
||||
if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
|
||||
if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
|
||||
if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
|
||||
if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
|
||||
if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
|
||||
if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
|
||||
if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
|
||||
if (pm1_sts & (1 << 15))
|
||||
printk(BIOS_DEBUG, "WAK ");
|
||||
if (pm1_sts & (1 << 14))
|
||||
printk(BIOS_DEBUG, "PCIEXPWAK ");
|
||||
if (pm1_sts & (1 << 11))
|
||||
printk(BIOS_DEBUG, "PRBTNOR ");
|
||||
if (pm1_sts & (1 << 10))
|
||||
printk(BIOS_DEBUG, "RTC ");
|
||||
if (pm1_sts & (1 << 8))
|
||||
printk(BIOS_DEBUG, "PWRBTN ");
|
||||
if (pm1_sts & (1 << 5))
|
||||
printk(BIOS_DEBUG, "GBL ");
|
||||
if (pm1_sts & (1 << 4))
|
||||
printk(BIOS_DEBUG, "BM ");
|
||||
if (pm1_sts & (1 << 0))
|
||||
printk(BIOS_DEBUG, "TMROF ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
|
@ -86,26 +94,46 @@ static u32 reset_smi_status(void)
|
|||
static void dump_smi_status(u32 smi_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SMI_STS: ");
|
||||
if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
|
||||
if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
|
||||
if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
|
||||
if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
|
||||
if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
|
||||
if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
|
||||
if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
|
||||
if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
|
||||
if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
|
||||
if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
|
||||
if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
|
||||
if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
|
||||
if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
|
||||
if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
|
||||
if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
|
||||
if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
|
||||
if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
|
||||
if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
|
||||
if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
|
||||
if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
|
||||
if (smi_sts & (1 << 26))
|
||||
printk(BIOS_DEBUG, "SPI ");
|
||||
if (smi_sts & (1 << 25))
|
||||
printk(BIOS_DEBUG, "EL_SMI ");
|
||||
if (smi_sts & (1 << 21))
|
||||
printk(BIOS_DEBUG, "MONITOR ");
|
||||
if (smi_sts & (1 << 20))
|
||||
printk(BIOS_DEBUG, "PCI_EXP_SMI ");
|
||||
if (smi_sts & (1 << 18))
|
||||
printk(BIOS_DEBUG, "INTEL_USB2 ");
|
||||
if (smi_sts & (1 << 17))
|
||||
printk(BIOS_DEBUG, "LEGACY_USB2 ");
|
||||
if (smi_sts & (1 << 16))
|
||||
printk(BIOS_DEBUG, "SMBUS_SMI ");
|
||||
if (smi_sts & (1 << 15))
|
||||
printk(BIOS_DEBUG, "SERIRQ_SMI ");
|
||||
if (smi_sts & (1 << 14))
|
||||
printk(BIOS_DEBUG, "PERIODIC ");
|
||||
if (smi_sts & (1 << 13))
|
||||
printk(BIOS_DEBUG, "TCO ");
|
||||
if (smi_sts & (1 << 12))
|
||||
printk(BIOS_DEBUG, "DEVMON ");
|
||||
if (smi_sts & (1 << 11))
|
||||
printk(BIOS_DEBUG, "MCSMI ");
|
||||
if (smi_sts & (1 << 10))
|
||||
printk(BIOS_DEBUG, "GPI ");
|
||||
if (smi_sts & (1 << 9))
|
||||
printk(BIOS_DEBUG, "GPE0 ");
|
||||
if (smi_sts & (1 << 8))
|
||||
printk(BIOS_DEBUG, "PM1 ");
|
||||
if (smi_sts & (1 << 6))
|
||||
printk(BIOS_DEBUG, "SWSMI_TMR ");
|
||||
if (smi_sts & (1 << 5))
|
||||
printk(BIOS_DEBUG, "APM ");
|
||||
if (smi_sts & (1 << 4))
|
||||
printk(BIOS_DEBUG, "SLP_SMI ");
|
||||
if (smi_sts & (1 << 3))
|
||||
printk(BIOS_DEBUG, "LEGACY_USB ");
|
||||
if (smi_sts & (1 << 2))
|
||||
printk(BIOS_DEBUG, "BIOS ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
|
@ -129,23 +157,38 @@ static void dump_gpe0_status(u32 gpe0_sts)
|
|||
{
|
||||
int i;
|
||||
printk(BIOS_DEBUG, "GPE0_STS: ");
|
||||
for (i=31; i>= 16; i--) {
|
||||
if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
|
||||
for (i = 31; i >= 16; i--) {
|
||||
if (gpe0_sts & (1 << i))
|
||||
printk(BIOS_DEBUG, "GPIO%d ", (i-16));
|
||||
}
|
||||
if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
|
||||
if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
|
||||
if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
|
||||
if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
|
||||
if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
|
||||
if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
|
||||
if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
|
||||
if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
|
||||
if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
|
||||
if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
|
||||
if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
|
||||
if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
|
||||
if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
|
||||
if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
|
||||
if (gpe0_sts & (1 << 14))
|
||||
printk(BIOS_DEBUG, "USB4 ");
|
||||
if (gpe0_sts & (1 << 13))
|
||||
printk(BIOS_DEBUG, "PME_B0 ");
|
||||
if (gpe0_sts & (1 << 12))
|
||||
printk(BIOS_DEBUG, "USB3 ");
|
||||
if (gpe0_sts & (1 << 11))
|
||||
printk(BIOS_DEBUG, "PME ");
|
||||
if (gpe0_sts & (1 << 10))
|
||||
printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
|
||||
if (gpe0_sts & (1 << 9))
|
||||
printk(BIOS_DEBUG, "PCI_EXP ");
|
||||
if (gpe0_sts & (1 << 8))
|
||||
printk(BIOS_DEBUG, "RI ");
|
||||
if (gpe0_sts & (1 << 7))
|
||||
printk(BIOS_DEBUG, "SMB_WAK ");
|
||||
if (gpe0_sts & (1 << 6))
|
||||
printk(BIOS_DEBUG, "TCO_SCI ");
|
||||
if (gpe0_sts & (1 << 5))
|
||||
printk(BIOS_DEBUG, "AC97 ");
|
||||
if (gpe0_sts & (1 << 4))
|
||||
printk(BIOS_DEBUG, "USB2 ");
|
||||
if (gpe0_sts & (1 << 3))
|
||||
printk(BIOS_DEBUG, "USB1 ");
|
||||
if (gpe0_sts & (1 << 2))
|
||||
printk(BIOS_DEBUG, "HOT_PLUG ");
|
||||
if (gpe0_sts & (1 << 0))
|
||||
printk(BIOS_DEBUG, "THRM ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
|
@ -169,8 +212,9 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
|
|||
{
|
||||
int i;
|
||||
printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
|
||||
for (i=15; i>= 0; i--) {
|
||||
if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
|
||||
for (i = 15; i >= 0; i--) {
|
||||
if (alt_gp_smi_sts & (1 << i))
|
||||
printk(BIOS_DEBUG, "GPI%d ", i);
|
||||
}
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
|
@ -199,19 +243,32 @@ static u32 reset_tco_status(void)
|
|||
static void dump_tco_status(u32 tco_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "TCO_STS: ");
|
||||
if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
|
||||
if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
|
||||
if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
|
||||
if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
|
||||
if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
|
||||
if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
|
||||
if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
|
||||
if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
|
||||
if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
|
||||
if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
|
||||
if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
|
||||
if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
|
||||
if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
|
||||
if (tco_sts & (1 << 20))
|
||||
printk(BIOS_DEBUG, "SMLINK_SLV ");
|
||||
if (tco_sts & (1 << 18))
|
||||
printk(BIOS_DEBUG, "BOOT ");
|
||||
if (tco_sts & (1 << 17))
|
||||
printk(BIOS_DEBUG, "SECOND_TO ");
|
||||
if (tco_sts & (1 << 16))
|
||||
printk(BIOS_DEBUG, "INTRD_DET ");
|
||||
if (tco_sts & (1 << 12))
|
||||
printk(BIOS_DEBUG, "DMISERR ");
|
||||
if (tco_sts & (1 << 10))
|
||||
printk(BIOS_DEBUG, "DMISMI ");
|
||||
if (tco_sts & (1 << 9))
|
||||
printk(BIOS_DEBUG, "DMISCI ");
|
||||
if (tco_sts & (1 << 8))
|
||||
printk(BIOS_DEBUG, "BIOSWR ");
|
||||
if (tco_sts & (1 << 7))
|
||||
printk(BIOS_DEBUG, "NEWCENTURY ");
|
||||
if (tco_sts & (1 << 3))
|
||||
printk(BIOS_DEBUG, "TIMEOUT ");
|
||||
if (tco_sts & (1 << 2))
|
||||
printk(BIOS_DEBUG, "TCO_INT ");
|
||||
if (tco_sts & (1 << 1))
|
||||
printk(BIOS_DEBUG, "SW_TCO ");
|
||||
if (tco_sts & (1 << 0))
|
||||
printk(BIOS_DEBUG, "NMI2SMI ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -99,14 +99,22 @@ static u16 reset_pm1_status(void)
|
|||
static void dump_pm1_status(u16 pm1_sts)
|
||||
{
|
||||
printk(BIOS_SPEW, "PM1_STS: ");
|
||||
if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
|
||||
if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
|
||||
if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
|
||||
if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
|
||||
if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
|
||||
if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
|
||||
if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
|
||||
if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
|
||||
if (pm1_sts & (1 << 15))
|
||||
printk(BIOS_SPEW, "WAK ");
|
||||
if (pm1_sts & (1 << 14))
|
||||
printk(BIOS_SPEW, "PCIEXPWAK ");
|
||||
if (pm1_sts & (1 << 11))
|
||||
printk(BIOS_SPEW, "PRBTNOR ");
|
||||
if (pm1_sts & (1 << 10))
|
||||
printk(BIOS_SPEW, "RTC ");
|
||||
if (pm1_sts & (1 << 8))
|
||||
printk(BIOS_SPEW, "PWRBTN ");
|
||||
if (pm1_sts & (1 << 5))
|
||||
printk(BIOS_SPEW, "GBL ");
|
||||
if (pm1_sts & (1 << 4))
|
||||
printk(BIOS_SPEW, "BM ");
|
||||
if (pm1_sts & (1 << 0))
|
||||
printk(BIOS_SPEW, "TMROF ");
|
||||
printk(BIOS_SPEW, "\n");
|
||||
int reg16 = inw(pmbase + PM1_EN);
|
||||
printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
|
||||
|
|
@ -130,26 +138,46 @@ static u32 reset_smi_status(void)
|
|||
static void dump_smi_status(u32 smi_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SMI_STS: ");
|
||||
if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
|
||||
if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
|
||||
if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
|
||||
if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
|
||||
if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
|
||||
if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
|
||||
if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
|
||||
if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
|
||||
if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
|
||||
if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
|
||||
if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
|
||||
if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
|
||||
if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
|
||||
if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
|
||||
if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
|
||||
if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
|
||||
if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
|
||||
if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
|
||||
if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
|
||||
if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
|
||||
if (smi_sts & (1 << 26))
|
||||
printk(BIOS_DEBUG, "SPI ");
|
||||
if (smi_sts & (1 << 25))
|
||||
printk(BIOS_DEBUG, "EL_SMI ");
|
||||
if (smi_sts & (1 << 21))
|
||||
printk(BIOS_DEBUG, "MONITOR ");
|
||||
if (smi_sts & (1 << 20))
|
||||
printk(BIOS_DEBUG, "PCI_EXP_SMI ");
|
||||
if (smi_sts & (1 << 18))
|
||||
printk(BIOS_DEBUG, "INTEL_USB2 ");
|
||||
if (smi_sts & (1 << 17))
|
||||
printk(BIOS_DEBUG, "LEGACY_USB2 ");
|
||||
if (smi_sts & (1 << 16))
|
||||
printk(BIOS_DEBUG, "SMBUS_SMI ");
|
||||
if (smi_sts & (1 << 15))
|
||||
printk(BIOS_DEBUG, "SERIRQ_SMI ");
|
||||
if (smi_sts & (1 << 14))
|
||||
printk(BIOS_DEBUG, "PERIODIC ");
|
||||
if (smi_sts & (1 << 13))
|
||||
printk(BIOS_DEBUG, "TCO ");
|
||||
if (smi_sts & (1 << 12))
|
||||
printk(BIOS_DEBUG, "DEVMON ");
|
||||
if (smi_sts & (1 << 11))
|
||||
printk(BIOS_DEBUG, "MCSMI ");
|
||||
if (smi_sts & (1 << 10))
|
||||
printk(BIOS_DEBUG, "GPI ");
|
||||
if (smi_sts & (1 << 9))
|
||||
printk(BIOS_DEBUG, "GPE0 ");
|
||||
if (smi_sts & (1 << 8))
|
||||
printk(BIOS_DEBUG, "PM1 ");
|
||||
if (smi_sts & (1 << 6))
|
||||
printk(BIOS_DEBUG, "SWSMI_TMR ");
|
||||
if (smi_sts & (1 << 5))
|
||||
printk(BIOS_DEBUG, "APM ");
|
||||
if (smi_sts & (1 << 4))
|
||||
printk(BIOS_DEBUG, "SLP_SMI ");
|
||||
if (smi_sts & (1 << 3))
|
||||
printk(BIOS_DEBUG, "LEGACY_USB ");
|
||||
if (smi_sts & (1 << 2))
|
||||
printk(BIOS_DEBUG, "BIOS ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
|
@ -173,23 +201,38 @@ static void dump_gpe0_status(u32 gpe0_sts)
|
|||
{
|
||||
int i;
|
||||
printk(BIOS_DEBUG, "GPE0_STS: ");
|
||||
for (i=31; i>= 16; i--) {
|
||||
if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
|
||||
for (i = 31; i >= 16; i--) {
|
||||
if (gpe0_sts & (1 << i))
|
||||
printk(BIOS_DEBUG, "GPIO%d ", (i-16));
|
||||
}
|
||||
if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
|
||||
if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
|
||||
if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
|
||||
if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
|
||||
if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
|
||||
if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
|
||||
if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
|
||||
if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
|
||||
if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
|
||||
if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
|
||||
if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
|
||||
if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
|
||||
if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
|
||||
if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
|
||||
if (gpe0_sts & (1 << 14))
|
||||
printk(BIOS_DEBUG, "USB4 ");
|
||||
if (gpe0_sts & (1 << 13))
|
||||
printk(BIOS_DEBUG, "PME_B0 ");
|
||||
if (gpe0_sts & (1 << 12))
|
||||
printk(BIOS_DEBUG, "USB3 ");
|
||||
if (gpe0_sts & (1 << 11))
|
||||
printk(BIOS_DEBUG, "PME ");
|
||||
if (gpe0_sts & (1 << 10))
|
||||
printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
|
||||
if (gpe0_sts & (1 << 9))
|
||||
printk(BIOS_DEBUG, "PCI_EXP ");
|
||||
if (gpe0_sts & (1 << 8))
|
||||
printk(BIOS_DEBUG, "RI ");
|
||||
if (gpe0_sts & (1 << 7))
|
||||
printk(BIOS_DEBUG, "SMB_WAK ");
|
||||
if (gpe0_sts & (1 << 6))
|
||||
printk(BIOS_DEBUG, "TCO_SCI ");
|
||||
if (gpe0_sts & (1 << 5))
|
||||
printk(BIOS_DEBUG, "AC97 ");
|
||||
if (gpe0_sts & (1 << 4))
|
||||
printk(BIOS_DEBUG, "USB2 ");
|
||||
if (gpe0_sts & (1 << 3))
|
||||
printk(BIOS_DEBUG, "USB1 ");
|
||||
if (gpe0_sts & (1 << 2))
|
||||
printk(BIOS_DEBUG, "HOT_PLUG ");
|
||||
if (gpe0_sts & (1 << 0))
|
||||
printk(BIOS_DEBUG, "THRM ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
|
@ -215,19 +258,32 @@ static u32 reset_tco_status(void)
|
|||
static void dump_tco_status(u32 tco_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "TCO_STS: ");
|
||||
if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
|
||||
if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
|
||||
if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
|
||||
if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
|
||||
if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
|
||||
if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
|
||||
if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
|
||||
if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
|
||||
if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
|
||||
if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
|
||||
if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
|
||||
if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
|
||||
if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
|
||||
if (tco_sts & (1 << 20))
|
||||
printk(BIOS_DEBUG, "SMLINK_SLV ");
|
||||
if (tco_sts & (1 << 18))
|
||||
printk(BIOS_DEBUG, "BOOT ");
|
||||
if (tco_sts & (1 << 17))
|
||||
printk(BIOS_DEBUG, "SECOND_TO ");
|
||||
if (tco_sts & (1 << 16))
|
||||
printk(BIOS_DEBUG, "INTRD_DET ");
|
||||
if (tco_sts & (1 << 12))
|
||||
printk(BIOS_DEBUG, "DMISERR ");
|
||||
if (tco_sts & (1 << 10))
|
||||
printk(BIOS_DEBUG, "DMISMI ");
|
||||
if (tco_sts & (1 << 9))
|
||||
printk(BIOS_DEBUG, "DMISCI ");
|
||||
if (tco_sts & (1 << 8))
|
||||
printk(BIOS_DEBUG, "BIOSWR ");
|
||||
if (tco_sts & (1 << 7))
|
||||
printk(BIOS_DEBUG, "NEWCENTURY ");
|
||||
if (tco_sts & (1 << 3))
|
||||
printk(BIOS_DEBUG, "TIMEOUT ");
|
||||
if (tco_sts & (1 << 2))
|
||||
printk(BIOS_DEBUG, "TCO_INT ");
|
||||
if (tco_sts & (1 << 1))
|
||||
printk(BIOS_DEBUG, "SW_TCO ");
|
||||
if (tco_sts & (1 << 0))
|
||||
printk(BIOS_DEBUG, "NMI2SMI ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
|
@ -325,14 +381,17 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
*/
|
||||
|
||||
switch (slp_typ) {
|
||||
case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
|
||||
case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
|
||||
case ACPI_S0:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
|
||||
case ACPI_S1:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
|
||||
case ACPI_S3:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
|
||||
/* Invalidate the cache before going to S3 */
|
||||
wbinvd();
|
||||
break;
|
||||
case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
|
||||
case ACPI_S4:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
|
||||
case ACPI_S5:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
|
||||
|
||||
|
|
@ -342,17 +401,17 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
* "KEEP", switch to "OFF" - KEEP is software emulated
|
||||
*/
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
|
||||
if (s5pwr == MAINBOARD_POWER_ON) {
|
||||
if (s5pwr == MAINBOARD_POWER_ON)
|
||||
reg8 &= ~1;
|
||||
} else {
|
||||
else
|
||||
reg8 |= 1;
|
||||
}
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
|
||||
|
||||
/* also iterates over all bridges on bus 0 */
|
||||
busmaster_disable_on_bus(0);
|
||||
break;
|
||||
default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
|
||||
}
|
||||
|
||||
#if !CONFIG_SMM_TSEG
|
||||
|
|
@ -360,7 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
* will never be unlocked because the next outl will switch off the CPU.
|
||||
* This might open a small race between the smi_release_lock() and the outl()
|
||||
* for other SMI handlers. Not sure if this could cause trouble. */
|
||||
if (slp_typ == ACPI_S3)
|
||||
if (slp_typ == ACPI_S3)
|
||||
smi_release_lock();
|
||||
#endif
|
||||
|
||||
|
|
@ -481,7 +540,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
|
|||
mainboard_smi_gpi(reg16);
|
||||
|
||||
if (reg16)
|
||||
printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
|
||||
printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
|
||||
}
|
||||
|
||||
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
|
||||
|
|
@ -509,7 +568,8 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
|
|||
if (!tco_sts)
|
||||
return;
|
||||
|
||||
if (tco_sts & (1 << 8)) { // BIOSWR
|
||||
if (tco_sts & (1 << 8)) {
|
||||
/* BIOSWR */
|
||||
u8 bios_cntl;
|
||||
|
||||
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||||
|
|
@ -560,7 +620,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
|
|||
RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
|
||||
|
||||
trap_cycle = RCBA32(0x1e10);
|
||||
for (i=16; i<20; i++) {
|
||||
for (i = 16; i < 20; i++) {
|
||||
if (trap_cycle & (1 << i))
|
||||
mask |= (0xff << ((i - 16) << 2));
|
||||
}
|
||||
|
|
@ -579,7 +639,9 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
|
|||
/* IOTRAP(0) SMIC: currently unused */
|
||||
|
||||
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
|
||||
for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
|
||||
for (i = 0; i < 4; i++)
|
||||
if (IOTRAP(i))
|
||||
printk(BIOS_DEBUG, " TRAP = %d\n", i);
|
||||
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
|
||||
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
|
||||
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
|
||||
|
|
@ -666,8 +728,6 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
|
|||
}
|
||||
}
|
||||
|
||||
if (dump) {
|
||||
if (dump)
|
||||
dump_smi_status(smi_sts);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,7 +42,8 @@ static void usb_init(struct device *dev)
|
|||
printk(BIOS_DEBUG, "done.\n");
|
||||
}
|
||||
|
||||
static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
static void usb_set_subsystem(device_t dev, unsigned int vendor,
|
||||
unsigned int device)
|
||||
{
|
||||
if (!vendor || !device) {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
|
|
|
|||
|
|
@ -58,7 +58,8 @@ static void usb_ehci_init(struct device *dev)
|
|||
printk(BIOS_DEBUG, "done.\n");
|
||||
}
|
||||
|
||||
static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
static void usb_ehci_set_subsystem(device_t dev, unsigned int vendor,
|
||||
unsigned int device)
|
||||
{
|
||||
u8 access_cntl;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue