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soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix 

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
>> iasl -d SSDT # to generate SSDT.dsl

Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Subrata Banik 2019-01-30 18:44:09 +05:30
parent c6c4d00182
commit 3f559d960c
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/icelake/acpi.c
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@ -119,13 +119,13 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
},
};
static int cstate_set_s0ix[] = {
static int cstate_set_non_s0ix[] = {
C_STATE_C1E,
C_STATE_C6_LONG_LAT,
C_STATE_C7S_LONG_LAT
};
static int cstate_set_non_s0ix[] = {
static int cstate_set_s0ix[] = {
C_STATE_C1E,
C_STATE_C7S_LONG_LAT,
C_STATE_C10