mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQ

Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.

This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.

Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie 2018-09-26 21:30:59 +00:00 committed by Patrick Georgi
parent ecf6531c47
commit 3f59f082e3
3 changed files with 7 additions and 1 deletions

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@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = {
/* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */
PAD_CFG_GPO(GPP_D16, 0, DEEP), PAD_CFG_GPO(GPP_D16, 0, DEEP),
/* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */
PAD_CFG_NC(GPP_D17), PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST),
/* D18 : DMIC_DATA1 ==> TP131 */ /* D18 : DMIC_DATA1 ==> TP131 */
PAD_CFG_NC(GPP_D18), PAD_CFG_NC(GPP_D18),
/* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */

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@ -79,4 +79,7 @@
#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ #define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */
#define EC_ENABLE_CBAS_DEVICE /* Enable "Base Attached Switch" device */ #define EC_ENABLE_CBAS_DEVICE /* Enable "Base Attached Switch" device */
/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */
#define EC_ENABLE_SYNC_IRQ
#endif /* __MAINBOARD_EC_H__ */ #endif /* __MAINBOARD_EC_H__ */

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@ -34,6 +34,9 @@
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK #define GPE_EC_WAKE GPE0_LAN_WAK
/* EC sync irq is GPP_D12 */
#define EC_SYNC_IRQ GPP_D17_IRQ
/* eSPI virtual wire reporting */ /* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI #define EC_SCI_GPI GPE0_ESPI