AMD F14 Northbridge updates
This change is warning and whitespace fixes in the northbridge code for AMD Family 14 rev C0 cpu update. This does not address warnings in the mainboard, Agesa, Cimx, or southbridge code. Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/134 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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@ -17,6 +17,10 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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#
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config CONSOLE_VGA_MULTI
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bool
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default n
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source src/northbridge/amd/agesa/family10/Kconfig
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source src/northbridge/amd/agesa/family10/Kconfig
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source src/northbridge/amd/agesa/family12/Kconfig
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source src/northbridge/amd/agesa/family12/Kconfig
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source src/northbridge/amd/agesa/family14/Kconfig
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source src/northbridge/amd/agesa/family14/Kconfig
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@ -33,6 +33,7 @@
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#include "chip.h"
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#include "chip.h"
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#include "northbridge.h"
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#include "northbridge.h"
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#include "SbEarly.h"
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#include "agesawrapper.h"
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#include "agesawrapper.h"
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//#define FX_DEVS NODE_NUMS
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//#define FX_DEVS NODE_NUMS
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@ -427,7 +428,7 @@ static void set_resource(device_t dev, struct resource *resource,
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}
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}
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#if CONFIG_CONSOLE_VGA_MULTI == 1
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#if CONFIG_CONSOLE_VGA_MULTI
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extern device_t vga_pri; // the primary vga device, defined in device.c
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extern device_t vga_pri; // the primary vga device, defined in device.c
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#endif
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#endif
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@ -441,7 +442,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
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* we only deal with the 'first' vga card */
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* we only deal with the 'first' vga card */
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for (link = dev->link_list; link; link = link->next) {
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for (link = dev->link_list; link; link = link->next) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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#if CONFIG_CONSOLE_VGA_MULTI == 1
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#if CONFIG_CONSOLE_VGA_MULTI
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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link->secondary,link->subordinate);
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link->secondary,link->subordinate);
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/* We need to make sure the vga_pri is under the link */
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/* We need to make sure the vga_pri is under the link */
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@ -37,7 +37,7 @@ config MMCONF_BASE_ADDRESS
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config MMCONF_BUS_NUMBER
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config MMCONF_BUS_NUMBER
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int
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int
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default 16
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default 16
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config BOOTBLOCK_NORTHBRIDGE_INIT
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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string
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@ -31,6 +31,7 @@
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/lapic.h>
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#include "agesawrapper.h"
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#include "chip.h"
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#include "chip.h"
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#include "northbridge.h"
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#include "northbridge.h"
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#if CONFIG_AMD_SB_CIMX
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#if CONFIG_AMD_SB_CIMX
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@ -289,7 +290,6 @@ struct hw_mem_hole_info {
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static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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{
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{
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struct hw_mem_hole_info mem_hole;
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struct hw_mem_hole_info mem_hole;
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int i;
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mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
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mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
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mem_hole.node_id = -1;
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mem_hole.node_id = -1;
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@ -420,7 +420,7 @@ static void set_resource(device_t dev, struct resource *resource,
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}
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}
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#if CONFIG_CONSOLE_VGA_MULTI == 1
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#if CONFIG_CONSOLE_VGA_MULTI
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extern device_t vga_pri; // the primary vga device, defined in device.c
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extern device_t vga_pri; // the primary vga device, defined in device.c
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#endif
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#endif
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@ -434,7 +434,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
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* we only deal with the 'first' vga card */
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* we only deal with the 'first' vga card */
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for (link = dev->link_list; link; link = link->next) {
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for (link = dev->link_list; link; link = link->next) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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#if CONFIG_CONSOLE_VGA_MULTI == 1
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#if CONFIG_CONSOLE_VGA_MULTI
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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link->secondary,link->subordinate);
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link->secondary,link->subordinate);
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/* We need to make sure the vga_pri is under the link */
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/* We need to make sure the vga_pri is under the link */
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@ -548,7 +548,7 @@ static void domain_read_resources(device_t dev)
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static void domain_set_resources(device_t dev)
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static void domain_set_resources(device_t dev)
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{
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{
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printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
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printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
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printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev);
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printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n",(u32)dev);
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#if CONFIG_PCI_64BIT_PREF_MEM == 1
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#if CONFIG_PCI_64BIT_PREF_MEM == 1
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struct resource *io, *mem1, *mem2;
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struct resource *io, *mem1, *mem2;
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@ -556,7 +556,7 @@ static void domain_set_resources(device_t dev)
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#endif
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#endif
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unsigned long mmio_basek;
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unsigned long mmio_basek;
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u32 pci_tolm;
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u32 pci_tolm;
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int i, idx;
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int idx;
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struct bus *link;
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struct bus *link;
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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struct hw_mem_hole_info mem_hole;
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struct hw_mem_hole_info mem_hole;
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@ -574,9 +574,9 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
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mem2 = find_resource(dev, 2|(link->link_num<<2));
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mem2 = find_resource(dev, 2|(link->link_num<<2));
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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(u32)(mem1->base), (u32)(mem1->limit), (u32)(mem1->size), u32)(mem1->align));
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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(u32)(mem2->base), (u32)(mem2->limit), (u32)(mem2->size), (u32)(mem2->align));
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/* See if both resources have roughly the same limits */
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/* See if both resources have roughly the same limits */
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if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
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if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
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@ -676,7 +676,7 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
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}
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}
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printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_basek, basek, limitk);
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printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmio_basek, basek, limitk);
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/* split the region to accomodate pci memory space */
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/* split the region to accomodate pci memory space */
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if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
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if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
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@ -722,7 +722,7 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
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/* Leave some space for ACPI, PIRQ and MP tables */
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/* Leave some space for ACPI, PIRQ and MP tables */
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#if CONFIG_GFXUMA == 1
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#if CONFIG_GFXUMA == 1
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high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
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high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
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printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base);
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printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n",uma_memory_base);
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#else
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#else
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high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
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high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
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#endif
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#endif
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}
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}
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#endif
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#endif
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}
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}
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printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek);
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printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n",mmio_basek);
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printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size);
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printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size);
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#if CONFIG_GFXUMA == 1
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#if CONFIG_GFXUMA == 1
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printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
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printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
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static struct device_operations pci_domain_ops;
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static struct device_operations pci_domain_ops;
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static struct device_operations cpu_bus_ops;
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static struct device_operations cpu_bus_ops;
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device_t get_node_pci(u32 nodeid, u32 fn);
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#endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */
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#endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */
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