Update to Asrock E350m1 for AMD F14 C0
This updates the E350m1 Agesa wrapper code to fix an issue with AmdLateRunApTask. It now passes the function parameter through to the Agesa routine. There is also a change to the platform_cfg.h file that makes the definition of BIOS_SIZE dependent on whether or not it was defined earlier. Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/139 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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efdesign98
Marc Jones
parent
7b7b2c9ef9
commit
99b6674bd2
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@ -377,7 +377,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
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Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
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return Status;
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}
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@ -435,42 +435,6 @@ UINT32
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agesawrapper_amdinitlate (
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VOID
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)
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{
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AGESA_STATUS Status;
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AMD_INTERFACE_PARAMS AmdParamStruct = {0};
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AMD_LATE_PARAMS *AmdLateParams;
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return 0; // this causes bad ACPI SSDT, need to debug
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AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
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AmdParamStruct.AllocationMethod = PostMemDram;
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AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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AmdCreateStruct (&AmdParamStruct);
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AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
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Status = AmdInitLate (AmdLateParams);
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if (Status != AGESA_SUCCESS) {
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agesawrapper_amdreadeventlog();
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ASSERT(Status == AGESA_SUCCESS);
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}
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DmiTable = AmdLateParams->DmiTable;
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AcpiPstate = AmdLateParams->AcpiPState;
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AcpiSrat = AmdLateParams->AcpiSrat;
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AcpiSlit = AmdLateParams->AcpiSlit;
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AcpiWheaMce = AmdLateParams->AcpiWheaMce;
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AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
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AcpiAlib = AmdLateParams->AcpiAlib;
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AmdReleaseStruct (&AmdParamStruct);
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return (UINT32)Status;
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}
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UINT32
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agesawrapper_amdlaterunaptask (
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UINT32 Data,
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VOID *ConfigPtr
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)
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{
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AGESA_STATUS Status;
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AMD_LATE_PARAMS AmdLateParams;
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@ -485,20 +449,52 @@ agesawrapper_amdlaterunaptask (
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AmdLateParams.StdHeader.Func = 0;
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AmdLateParams.StdHeader.ImageBasePtr = 0;
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Status = AmdLateRunApTask (&AmdLateParams);
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Status = AmdInitLate (&AmdLateParams);
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if (Status != AGESA_SUCCESS) {
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agesawrapper_amdreadeventlog();
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ASSERT(Status == AGESA_SUCCESS);
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}
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DmiTable = AmdLateParams.DmiTable;
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AcpiPstate = AmdLateParams.AcpiPState;
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AcpiSrat = AmdLateParams.AcpiSrat;
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AcpiSlit = AmdLateParams.AcpiSlit;
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DmiTable = AmdLateParams.DmiTable;
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AcpiPstate = AmdLateParams.AcpiPState;
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AcpiSrat = AmdLateParams.AcpiSrat;
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AcpiSlit = AmdLateParams.AcpiSlit;
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AcpiWheaMce = AmdLateParams.AcpiWheaMce;
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AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
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AcpiAlib = AmdLateParams.AcpiAlib;
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AcpiWheaMce = AmdLateParams.AcpiWheaMce;
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AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
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AcpiAlib = AmdLateParams.AcpiAlib;
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return (UINT32)Status;
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}
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UINT32
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agesawrapper_amdlaterunaptask (
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UINT32 Func,
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UINT32 Data,
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VOID *ConfigPtr
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)
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{
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AGESA_STATUS Status;
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AP_EXE_PARAMS ApExeParams;
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LibAmdMemFill (&ApExeParams,
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0,
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sizeof (AP_EXE_PARAMS),
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&(ApExeParams.StdHeader));
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ApExeParams.StdHeader.AltImageBasePtr = 0;
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ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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ApExeParams.StdHeader.Func = 0;
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ApExeParams.StdHeader.ImageBasePtr = 0;
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ApExeParams.StdHeader.ImageBasePtr = 0;
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ApExeParams.FunctionNumber = Func;
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ApExeParams.RelatedDataBlock = ConfigPtr;
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Status = AmdLateRunApTask (&ApExeParams);
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if (Status != AGESA_SUCCESS) {
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agesawrapper_amdreadeventlog();
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ASSERT(Status == AGESA_SUCCESS);
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}
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return (UINT32)Status;
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}
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@ -86,6 +86,7 @@ UINT32 agesawrapper_amdinitmid (void);
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UINT32 agesawrapper_amdreadeventlog (void);
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UINT32 agesawrapper_amdinitmmio (void);
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UINT32 agesawrapper_amdinitcpuio (void);
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UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
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void *agesawrapper_getlateinitptr (int pick);
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#endif
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@ -36,14 +36,16 @@
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* bigger than 1M you have to set the ROM size outside CIMx module and
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* before AGESA module get call.
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*/
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#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
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#define BIOS_SIZE BIOS_SIZE_1M
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#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
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#define BIOS_SIZE BIOS_SIZE_2M
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#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
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#define BIOS_SIZE BIOS_SIZE_4M
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#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
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#define BIOS_SIZE BIOS_SIZE_8M
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#ifndef BIOS_SIZE
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#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
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#define BIOS_SIZE BIOS_SIZE_1M
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#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
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#define BIOS_SIZE BIOS_SIZE_2M
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#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
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#define BIOS_SIZE BIOS_SIZE_4M
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#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
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#define BIOS_SIZE BIOS_SIZE_8M
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#endif
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#endif
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/**
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@ -56,7 +58,7 @@
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/**
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* @def SB_HPET_TIMER
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* @breif
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* @brief
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* 0 - Disable hpet
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* 1 - Enable hpet
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*/
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@ -79,7 +81,7 @@
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/**
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* @def PCI_CLOCK_CTRL
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* @breif bit[0-4] used for PCI Slots Clock Control,
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* @brief bit[0-4] used for PCI Slots Clock Control,
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* 0 - disable
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* 1 - enable
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* PCI SLOT 0 define at BIT0
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@ -92,26 +94,26 @@
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/**
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* @def SATA_CONTROLLER
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* @breif INCHIP Sata Controller
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* @brief INCHIP Sata Controller
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*/
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#define SATA_CONTROLLER CIMX_OPTION_ENABLED
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/**
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* @def SATA_MODE
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* @breif INCHIP Sata Controller Mode
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* @brief INCHIP Sata Controller Mode
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* NOTE: DO NOT ALLOW SATA & IDE use same mode
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*/
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#define SATA_MODE NATIVE_IDE_MODE
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/**
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* @breif INCHIP Sata IDE Controller Mode
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* @brief INCHIP Sata IDE Controller Mode
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*/
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#define IDE_LEGACY_MODE 0
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#define IDE_NATIVE_MODE 1
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/**
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* @def SATA_IDE_MODE
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* @breif INCHIP Sata IDE Controller Mode
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* @brief INCHIP Sata IDE Controller Mode
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* NOTE: DO NOT ALLOW SATA & IDE use same mode
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*/
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#define SATA_IDE_MODE IDE_LEGACY_MODE
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@ -155,7 +157,7 @@
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#define AZALIA_ENABLE 2
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/**
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* @breif INCHIP HDA controller
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* @brief INCHIP HDA controller
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*/
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#define AZALIA_CONTROLLER AZALIA_AUTO
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