GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/i440bx,i82371: Remove wrapper spd_read_byte() 

Change-Id: Ib94ce73eb22c5b4b489dbd871279e8cd9a7010a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-01-07 12:10:02 +02:00
parent 93e08c75d3
commit 3f882fafa0
6 changed files with 13 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/asus/p2b-ds/romstage.c
View File

@ -24,11 +24,6 @@
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
void mainboard_romstage_entry(void)
{
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

5
src/mainboard/asus/p2b-ls/romstage.c
View File

@ -25,11 +25,6 @@
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
void mainboard_romstage_entry(void)
{
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

5
src/mainboard/asus/p2b/romstage.c
View File

@ -24,11 +24,6 @@
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
void mainboard_romstage_entry(void)
{
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

5
src/mainboard/asus/p3b-f/romstage.c
View File

@ -27,11 +27,6 @@
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
/*
* ASUS P3B-F specific SPD enable magic.
*

24
src/northbridge/intel/i440bx/raminit.c
View File

@ -25,6 +25,8 @@
#include "i440bx.h"
#include "raminit.h"
#include <southbridge/intel/i82371eb/i82371eb.h>
/*
* Macros and definitions
*/
@ -650,7 +652,7 @@ static void spd_enable_refresh(void)
reg = pci_read_config8(NB, DRAMC);
for (i = 0; i < DIMM_SOCKETS; i++) {
value = spd_read_byte(DIMM0 + i, SPD_REFRESH);
value = smbus_read_byte(DIMM0 + i, SPD_REFRESH);
if (value < 0)
continue;
reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
@ -694,8 +696,8 @@ static struct dimm_size spd_get_dimm_size(unsigned int device)
struct dimm_size sz;
int i, module_density, dimm_banks;
sz.side1 = 0;
module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
module_density = smbus_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
dimm_banks = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
/* Find the size of side1. */
/* Find the larger value. The larger value is always side1. */
@ -780,7 +782,7 @@ static void set_dram_row_attributes(void)
nbxecc >>= 2;
/* First check if a DIMM is actually present. */
value = spd_read_byte(device, SPD_MEMORY_TYPE);
value = smbus_read_byte(device, SPD_MEMORY_TYPE);
/* This is 440BX! We do EDO too! */
if (value == SPD_MEMORY_TYPE_EDO
|| value == SPD_MEMORY_TYPE_SDRAM) {
@ -801,21 +803,21 @@ static void set_dram_row_attributes(void)
dra = 0;
/* Columns */
col = spd_read_byte(device, SPD_NUM_COLUMNS);
col = smbus_read_byte(device, SPD_NUM_COLUMNS);
/*
* Is this an ECC DIMM? Actually will be a 2 if so.
* TODO: Other register than NBXCFG also needs this
* ECC information.
*/
value = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
value = smbus_read_byte(device, SPD_DIMM_CONFIG_TYPE);
/* Data width */
width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
width = smbus_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
/* Exclude error checking data width from page size calculations */
if (value) {
value = spd_read_byte(device,
value = smbus_read_byte(device,
SPD_ERROR_CHECKING_SDRAM_WIDTH);
width -= value;
/* ### ECC */
@ -831,7 +833,7 @@ static void set_dram_row_attributes(void)
* By registered, only the address and control lines need to be, which
* we can tell by reading SPD byte 21, bit 1.
*/
value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES);
PRINT_DEBUG("DIMM is ");
if ((value & MODULE_REGISTERED) == 0) {
@ -847,12 +849,12 @@ static void set_dram_row_attributes(void)
dra = (value >> 13);
/* Number of banks of DIMM (single or double sided). */
value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
value = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
/* Once we have dra, col is done and can be reused.
* So it's reused for number of banks.
*/
col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
col = smbus_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
if (value == 1) {
/*

1
src/northbridge/intel/i440bx/raminit.h
View File

@ -24,7 +24,6 @@ void enable_spd(void);
void disable_spd(void);
/* Function prototypes. */
int spd_read_byte(unsigned int device, unsigned int address);
void sdram_set_registers(void);
void sdram_set_spd_registers(void);
void sdram_enable(void);