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soc/intel/jsl: Use the common code to set the PchPmPwrCycDur 

This patch uses the common code to avoid violating the PCH EDS
recommendation for the PchPmPwrCycDur setting.

Change-Id: I8aba558082ff5bbe2c5b12e0e623c013548e6481
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45030
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya 2020-09-02 17:20:06 +05:30 committed by Patrick Georgi
parent 27413d3219
commit 3fc368d09b
1 changed files with 1 additions and 125 deletions
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126
src/soc/intel/jasperlake/fsp_params.c
View File

@ -7,6 +7,7 @@
#include <fsp/util.h>
#include <intelblocks/lpss.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/intel/common/vbt.h>
@ -42,38 +43,6 @@ static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_UART2
};
/* List of Minimum Assertion durations in microseconds */
enum min_assrt_dur {
MinAssrtDur0s = 0,
MinAssrtDur60us = 60,
MinAssrtDur1ms = 1000,
MinAssrtDur50ms = 50000,
MinAssrtDur98ms = 98000,
MinAssrtDur500ms = 500000,
MinAssrtDur1s = 1000000,
MinAssrtDur2s = 2000000,
MinAssrtDur3s = 3000000,
MinAssrtDur4s = 4000000,
};
/* Signal Assertion duration values */
struct cfg_assrt_dur {
/* Minimum assertion duration of SLP_A signal */
enum min_assrt_dur slp_a;
/* Minimum assertion duration of SLP_4 signal */
enum min_assrt_dur slp_s4;
/* Minimum assertion duration of SLP_3 signal */
enum min_assrt_dur slp_s3;
/* PCH PM Power Cycle duration */
enum min_assrt_dur pm_pwr_cyc_dur;
};
/* Default value of PchPmPwrCycDur */
#define PCH_PM_PWR_CYC_DUR 0
static void parse_devicetree(FSP_S_CONFIG *params)
{
const struct soc_intel_jasperlake_config *config = config_of_soc();
@ -109,99 +78,6 @@ static void parse_devicetree(FSP_S_CONFIG *params)
sizeof(config->SerialIoUartMode));
}
/* This function returns the highest assertion duration of the SLP_Sx assertion widths */
static enum min_assrt_dur get_high_assrt_width(const struct cfg_assrt_dur *cfg_assrt_dur)
{
enum min_assrt_dur max_assert_dur = cfg_assrt_dur->slp_s4;
if (max_assert_dur < cfg_assrt_dur->slp_s3)
max_assert_dur = cfg_assrt_dur->slp_s3;
if (max_assert_dur < cfg_assrt_dur->slp_a)
max_assert_dur = cfg_assrt_dur->slp_a;
return max_assert_dur;
}
/* This function converts assertion durations from register-encoded to microseconds */
static void get_min_assrt_dur(uint8_t slp_s4_min_assrt, uint8_t slp_s3_min_assrt,
uint8_t slp_a_min_assrt, uint8_t pm_pwr_cyc_dur,
struct cfg_assrt_dur *cfg_assrt_dur)
{
/*
* Ensure slp_x_dur_list[] elements in the devicetree config are in sync with
* FSP encoded values.
*/
/* slp_s4_assrt_dur_list : 1s, 1s(default), 2s, 3s, 4s */
const enum min_assrt_dur slp_s4_assrt_dur_list[] = {
MinAssrtDur1s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s
};
/* slp_s3_assrt_dur_list: 50ms, 60us, 1ms, 50ms (Default), 2s */
const enum min_assrt_dur slp_s3_assrt_dur_list[] = {
MinAssrtDur50ms, MinAssrtDur60us, MinAssrtDur1ms, MinAssrtDur50ms, MinAssrtDur2s
};
/* slp_a_assrt_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */
const enum min_assrt_dur slp_a_assrt_dur_list[] = {
MinAssrtDur2s, MinAssrtDur0s, MinAssrtDur4s, MinAssrtDur98ms, MinAssrtDur2s
};
/* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */
const enum min_assrt_dur pm_pwr_cyc_dur_list[] = {
MinAssrtDur4s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s
};
/* Get signal assertion width */
if (slp_s4_min_assrt < ARRAY_SIZE(slp_s4_assrt_dur_list))
cfg_assrt_dur->slp_s4 = slp_s4_assrt_dur_list[slp_s4_min_assrt];
if (slp_s3_min_assrt < ARRAY_SIZE(slp_s3_assrt_dur_list))
cfg_assrt_dur->slp_s3 = slp_s3_assrt_dur_list[slp_s3_min_assrt];
if (slp_a_min_assrt < ARRAY_SIZE(slp_a_assrt_dur_list))
cfg_assrt_dur->slp_a = slp_a_assrt_dur_list[slp_a_min_assrt];
if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list))
cfg_assrt_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur];
}
/* This function ensures that the duration programmed in the PchPmPwrCycDur will never be
* smaller than the SLP_Sx assertion widths.
* If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the
* default value PCH_PM_PWR_CYC_DUR.
*/
static uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assrt, uint8_t slp_s3_min_assrt,
uint8_t slp_a_min_assrt, uint8_t pm_pwr_cyc_dur)
{
/* Set default values for the minimum assertion duration */
struct cfg_assrt_dur cfg_assrt_dur = {
.slp_a = MinAssrtDur2s,
.slp_s4 = MinAssrtDur1s,
.slp_s3 = MinAssrtDur50ms,
.pm_pwr_cyc_dur = MinAssrtDur4s
};
enum min_assrt_dur high_assrt_width;
/* Convert assertion durations from register-encoded to microseconds */
get_min_assrt_dur(slp_s4_min_assrt, slp_s3_min_assrt, slp_a_min_assrt, pm_pwr_cyc_dur,
&cfg_assrt_dur);
/* Get the highest assertion duration among PCH EDS specified signals for pwr_cyc_dur */
high_assrt_width = get_high_assrt_width(&cfg_assrt_dur);
if (cfg_assrt_dur.pm_pwr_cyc_dur >= high_assrt_width)
return pm_pwr_cyc_dur;
printk(BIOS_DEBUG,
"Set PmPwrCycDur to 4s as configured PmPwrCycDur (%d) violates PCH EDS "
"spec\n", pm_pwr_cyc_dur);
return PCH_PM_PWR_CYC_DUR;
}
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{