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google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low 

Adapted from chromium commit adcb858
[cyan: Configure WLAN_CLKREQ as GPIO and always assert low]

This is a workaround for issue b/35648315 as proposed by Intel to
ensure that WLAN_CLKREQ always stays low.

BUG=b:35648315

Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1055652
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Tested-by: Rajat Jain <rajatja@chromium.org>

Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier 2018-07-31 16:56:37 -05:00 committed by Patrick Georgi
parent eb7940d8b0
commit 404962f32c
1 changed files with 3 additions and 1 deletions
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4
src/mainboard/google/cyan/variants/cyan/gpio.c
View File

@ -136,7 +136,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 90 PCIE_CLKREQ0B */
GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
/* Workaround for issue b/35648315: Program this as GPIO and always
assert it low. */
GPIO_OUT_LOW, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */