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google/cyan: Mask Audio IRQ on boot 

Adapted from chromium commit cf18ab6
[Strago: mask Audio IRQ on boot]

Do not start with audio interrupt unmasked; this causes interrupt storms
on newer kernels that no longer mask all interrupts when initializing
Cherryview pincontrol driver.

TEST=Boot various cyan boards with kernels 3.18 and 4.14;
verify everything works.

Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894688
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier 2018-07-31 16:53:43 -05:00 committed by Patrick Georgi
parent 0aa52739dd
commit eb7940d8b0
10 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/cyan/variants/celes/gpio.c
View File

@ -140,7 +140,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/cyan/gpio.c
View File

@ -138,7 +138,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/edgar/gpio.c
View File

@ -137,7 +137,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/kefka/gpio.c
View File

@ -137,7 +137,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/reks/gpio.c
View File

@ -139,7 +139,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/relm/gpio.c
View File

@ -140,7 +140,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/setzer/gpio.c
View File

@ -138,7 +138,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/terra/gpio.c
View File

@ -136,7 +136,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/ultima/gpio.c
View File

@ -139,7 +139,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */

2
src/mainboard/google/cyan/variants/wizpig/gpio.c
View File

@ -138,7 +138,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
Native_M1, /* 92 GP_SSP_2_CLK */
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */