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soc/amd/phoenix: Expand APOB to 256K 

APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE
regions to fit. This requires moving memory addresses around to prevent
overlapping memory linker errors.

TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds
all boards

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Fred Reitberger 2023-02-08 13:05:05 -05:00 committed by Felix Held
parent 0ef9d890fa
commit 4064677fde
5 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/birman/board_phoenix.fmd
View File

@ -3,6 +3,6 @@ FLASH@0xFF000000 16M {
EC 4K EC 4K
FMAP 4K FMAP 4K
COREBOOT(CBFS) COREBOOT(CBFS)
RW_MRC_CACHE 120K RW_MRC_CACHE 256K
} }
} }

2
src/mainboard/amd/birman/chromeos_phoenix.fmd
View File

@ -29,6 +29,6 @@ FLASH@0xFF000000 16M {
RW_NVRAM(PRESERVE) 20K RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 64K SMMSTORE(PRESERVE) 64K
RW_LEGACY(CBFS) RW_LEGACY(CBFS)
RW_MRC_CACHE(PRESERVE) 120K RW_MRC_CACHE(PRESERVE) 256K
} }
} }

2
src/mainboard/amd/mayan/board.fmd
View File

@ -3,6 +3,6 @@ FLASH@0xFF000000 16M {
EC 4K EC 4K
FMAP 4K FMAP 4K
COREBOOT(CBFS) COREBOOT(CBFS)
RW_MRC_CACHE 120K RW_MRC_CACHE 256K
} }
} }

2
src/mainboard/amd/mayan/chromeos.fmd
View File

@ -29,6 +29,6 @@ FLASH@0xFF000000 16M {
RW_NVRAM(PRESERVE) 20K RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 64K SMMSTORE(PRESERVE) 64K
RW_LEGACY(CBFS) RW_LEGACY(CBFS)
RW_MRC_CACHE(PRESERVE) 120K RW_MRC_CACHE(PRESERVE) 256K
} }
} }

10
src/soc/amd/phoenix/Kconfig
View File

@ -116,11 +116,11 @@ config PSP_APOB_DRAM_ADDRESS
config PSP_APOB_DRAM_SIZE config PSP_APOB_DRAM_SIZE
hex hex
default 0x1E000 default 0x40000
config PSP_SHAREDMEM_BASE config PSP_SHAREDMEM_BASE
hex hex
default 0x201F000 if VBOOT default 0x2041000 if VBOOT
default 0x0 default 0x0
help help
This variable defines the base address in DRAM memory where PSP copies This variable defines the base address in DRAM memory where PSP copies
@ -165,7 +165,7 @@ config C_ENV_BOOTBLOCK_SIZE
config ROMSTAGE_ADDR config ROMSTAGE_ADDR
hex hex
default 0x2040000 default 0x2060000
help help
Sets the address in DRAM where romstage should be loaded. Sets the address in DRAM where romstage should be loaded.
@ -177,7 +177,7 @@ config ROMSTAGE_SIZE
config FSP_M_ADDR config FSP_M_ADDR
hex hex
default 0x20C0000 default 0x20E0000
help help
Sets the address in DRAM where FSP-M should be loaded. cbfstool Sets the address in DRAM where FSP-M should be loaded. cbfstool
performs relocation of FSP-M to this address. performs relocation of FSP-M to this address.
@ -197,7 +197,7 @@ config FSP_TEMP_RAM_SIZE
config VERSTAGE_ADDR config VERSTAGE_ADDR
hex hex
depends on VBOOT_SEPARATE_VERSTAGE depends on VBOOT_SEPARATE_VERSTAGE
default 0x2180000 default 0x21A0000
help help
Sets the address in DRAM where verstage should be loaded if running Sets the address in DRAM where verstage should be loaded if running
as a separate stage on x86. as a separate stage on x86.