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vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release 

Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter,
and adds some fields to HOBs.

Update FspmUpd.h and HOB header files.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Zhang 2020-10-01 14:20:41 -07:00 committed by Angel Pons
parent 86b3bf10e6
commit 407d552e0c
3 changed files with 21 additions and 7 deletions
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23
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
View File

@ -700,19 +700,32 @@ typedef struct {
**/
UINT8 PchDciEn;
/** Offset 0x014D - SerialIoUartDebugEnable
/** Offset 0x014D - MeUmaEnable
Enable or disable ME UMA feature
**/
UINT8 MeUmaEnable;
/** Offset 0x014E - SerialIoUartDebugEnable
Enable SerialIo Uart debug library in FSP.
0:Disable, 1:Enable
**/
UINT8 SerialIoUartDebugEnable;
/** Offset 0x014E - ISA Serial Base selection
/** Offset 0x014F
**/
UINT8 UnusedUpdSpace2;
/** Offset 0x0150 - ISA Serial Base selection
Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
0x3F8, 0x2F8
**/
UINT16 SerialIoUartDebugIoBase;
/** Offset 0x0150
/** Offset 0x0152
**/
UINT8 UnusedUpdSpace3[2];
/** Offset 0x0154
**/
UINT8 ReservedMemoryInitUpd[16];
} FSPM_CONFIG;
@ -733,9 +746,9 @@ typedef struct {
**/
FSPM_CONFIG FspmConfig;
/** Offset 0x0160
/** Offset 0x0164
**/
UINT8 UnusedUpdSpace2[6];
UINT8 UnusedUpdSpace4[2];
/** Offset 0x0166
**/

1
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
View File

@ -209,6 +209,7 @@ typedef struct _STACK_RES {
uint64_t PciResourceMem64Base;
uint64_t PciResourceMem64Limit;
uint32_t VtdBarAddress;
uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack
} STACK_RES;
typedef struct {

4
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
View File

@ -124,7 +124,7 @@ struct ChannelDevice {
};
typedef struct socket {
UINT8 reserved1[1110];
UINT8 reserved1[1114];
struct ChannelDevice ChannelInfo[MAX_CH];
} MEMMAP_SOCKET;
@ -154,7 +154,7 @@ typedef struct SystemMemoryMapHob {
UINT32 MmiohBase; // MMIOH base in 64MB granularity
UINT8 reserved6[4];
UINT8 reserved6[5];
} SYSTEM_MEMORY_MAP_HOB;