intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP

Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15228
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/car/cache_as_ram_ht.inc

@@ -339,8 +339,12 @@ no_msr_11e:
 	post_code(0x2f)
 
 	/* Call romstage.c main function. */
-	call	main
-	addl	$4, %esp
+	call	romstage_main
+
+	/* Save return value from romstage_main. It contains the stack to use
+	 * after cache-as-ram is torn down. It also contains the information
+	 * for setting up MTRRs. */
+	movl	%eax, %ebx
 
 	post_code(0x30)
 
@@ -425,7 +429,8 @@ __main:
 	post_code(POST_PREPARE_RAMSTAGE)
 	cld			/* Clear direction flag. */
 
-	movl	$CONFIG_RAMTOP, %esp
+	/* Setup stack as indicated by return value from romstage_main(). */
+	movl	%ebx, %esp
 	movl	%esp, %ebp
 	call	copy_and_run
 

src/cpu/intel/model_106cx/Makefile.inc

@@ -2,4 +2,5 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+romstage-y += ../car/romstage.c
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin

src/cpu/intel/socket_LGA775/Makefile.inc

@@ -15,3 +15,4 @@ subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -10,3 +10,4 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+romstage-y += ../car/romstage.c

src/mainboard/aopen/dxplplusu/romstage.c

@@ -20,6 +20,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 
 #include <southbridge/intel/i82801dx/i82801dx.h>
 #include <northbridge/intel/e7505/raminit.h>
@@ -34,8 +35,7 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {
 		{

src/mainboard/gigabyte/ga-g41m-es2l/romstage.c

@@ -23,10 +23,10 @@
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <superio/ite/it8718f/it8718f.h>
 #include <superio/ite/common/ite.h>
 #include <lib.h>
-#include <cpu/intel/romstage.h>
 #include <arch/stages.h>
 #include <cbmem.h>
 
@@ -132,7 +132,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
 }
 
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	//                          ch0      ch1
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };

src/mainboard/intel/d510mo/romstage.c

@@ -24,6 +24,7 @@
 #include <northbridge/intel/pineview/raminit.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <cpu/x86/lapic.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 #include <superio/winbond/common/winbond.h>
@@ -33,7 +34,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
 
-#include <cpu/intel/romstage.h>
 
 /* Early mainboard specific GPIO setup */
 static void mb_gpio_init(void)
@@ -102,7 +102,7 @@ static void rcba_config(void)
 	RCBA32(0x3418) |= 1;
 }
 
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
 

src/mainboard/intel/d945gclf/romstage.c

@@ -28,6 +28,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
@@ -149,8 +150,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	int s3resume = 0, boot_mode = 0;
 

src/mainboard/iwave/iWRainbowG6/romstage.c

@@ -20,6 +20,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/cache.h>
+#include <cpu/intel/romstage.h>
 #include <arch/cpu.h>
 #include <console/console.h>
 #if 0
@@ -328,8 +329,7 @@ static void poulsbo_setup_Stage2Regs(void)
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	int boot_mode = 0;