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mb/lenovo/x200: Link gpio map instead of including a header 

Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.

This commit follows up on commit 7dee9745 with Change-Id
I88b5ef8e12ac606751952a493f626e1b146e98f7 ("mb/lenovo/x201: Link gpio
map instead of including a header").

Change-Id: Ibdb96deafbe422bf50fd2e1fc56a57ae53ccd5a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2017-04-05 12:05:12 +02:00 committed by Patrick Rudolph
parent 5a5f6a76ec
commit 40b0fc3f8b
3 changed files with 4 additions and 8 deletions
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1
src/mainboard/lenovo/x200/Makefile.inc
View File

@ -16,5 +16,6 @@
ramstage-y += dock.c
ramstage-y += cstates.c
ramstage-y += blc.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

7
src/mainboard/lenovo/x200/gpio.h → src/mainboard/lenovo/x200/gpio.c
View File

@ -11,9 +11,6 @@
* GNU General Public License for more details.
*/
#ifndef LENOVO_X200_GPIO_H
#define LENOVO_X200_GPIO_H
#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
@ -296,7 +293,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio63 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_map x200_gpio_map = {
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
@ -310,5 +307,3 @@ const struct pch_gpio_map x200_gpio_map = {
.level = &pch_gpio_set2_level,
},
};
#endif

4
src/mainboard/lenovo/x200/romstage.c
View File

@ -27,9 +27,9 @@
#include <lib.h>
#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
#include "gpio.h"
#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@ -79,7 +79,7 @@ void mainboard_romstage_entry(unsigned long bist)
gm45_early_reset();
}
setup_pch_gpios(&x200_gpio_map);
setup_pch_gpios(&mainboard_gpio_map);
/* ASPM related setting, set early by original BIOS. */
DMIBAR16(0x204) &= ~(3 << 10);