set irq options.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -133,6 +133,9 @@ chip northbridge/amd/gx2
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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register "lpc_serirq_enable" = "0x80" # enabled with default timing
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register "lpc_irq" = "((1<<3)|(1<<4))" # IRQ 3 & 4
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register "enable_gpio0_inta" = "1"
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device pci d.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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