soc/qualcomm/common/qspi: Add support for common QSPI driver

copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder.

This common QSPI driver works in master mode and provides read/write
operation for the slave devices like flash.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>

src/soc/qualcomm/common/include/soc/qspi_common.h

@@ -3,10 +3,10 @@
 #include <soc/addressmap.h>
 #include <spi-generic.h>
 
-#ifndef __SOC_QUALCOMM_SC7180_QSPI_H__
-#define __SOC_QUALCOMM_SC7180_QSPI_H__
+#ifndef __SOC_QUALCOMM_QSPI_H__
+#define __SOC_QUALCOMM_QSPI_H__
 
-struct sc7180_qspi_regs {
+struct qcom_qspi_regs {
 	u32 mstr_cfg;
 	u32 ahb_mstr_cfg;
 	u32 reserve_0;
@@ -28,8 +28,8 @@ struct sc7180_qspi_regs {
 	u32 rd_fifo[16];
 };
 
-check_member(sc7180_qspi_regs, rd_fifo, 0x50);
-static struct sc7180_qspi_regs * const sc7180_qspi = (void *) QSPI_BASE;
+check_member(qcom_qspi_regs, rd_fifo, 0x50);
+static struct qcom_qspi_regs * const qcom_qspi = (void *) QSPI_BASE;
 
 // MSTR_CONFIG register
 
@@ -98,11 +98,11 @@ static struct sc7180_qspi_regs * const sc7180_qspi = (void *) QSPI_BASE;
 #define QSPI_MAX_PACKET_COUNT 0xFFC0
 
 void quadspi_init(uint32_t hz);
-int sc7180_claim_bus(const struct spi_slave *slave);
-int sc7180_setup_bus(const struct spi_slave *slave);
-void sc7180_release_bus(const struct spi_slave *slave);
-int sc7180_xfer(const struct spi_slave *slave, const void *dout,
+int qspi_claim_bus(const struct spi_slave *slave);
+int qspi_setup_bus(const struct spi_slave *slave);
+void qspi_release_bus(const struct spi_slave *slave);
+int qspi_xfer(const struct spi_slave *slave, const void *dout,
 		size_t out_bytes, void *din, size_t in_bytes);
-int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout,
+int qspi_xfer_dual(const struct spi_slave *slave, const void *dout,
 		     size_t out_bytes, void *din, size_t in_bytes);
-#endif /* __SOC_QUALCOMM_SC7180_QSPI_H__ */
+#endif /* __SOC_QUALCOMM_QSPI_H__ */

src/soc/qualcomm/common/qspi.c

@@ -5,7 +5,7 @@
 #include <arch/cache.h>
 #include <device/mmio.h>
 #include <soc/addressmap.h>
-#include <soc/qspi.h>
+#include <soc/qspi_common.h>
 #include <soc/gpio.h>
 #include <soc/clock.h>
 #include <symbols.h>
@@ -65,11 +65,11 @@ static void dma_transfer_chain(struct cmd_desc *chain)
 {
 	uint32_t mstr_int_status;
 
-	write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF);
-	write32(&sc7180_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain);
+	write32(&qcom_qspi->mstr_int_sts, 0xFFFFFFFF);
+	write32(&qcom_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain);
 
 	while (1) {
-		mstr_int_status = read32(&sc7180_qspi->mstr_int_sts);
+		mstr_int_status = read32(&qcom_qspi->mstr_int_sts);
 		if (mstr_int_status & DMA_CHAIN_DONE)
 			break;
 	}
@@ -138,20 +138,20 @@ static struct cmd_desc *allocate_descriptor(void)
 
 static void cs_change(enum cs_state state)
 {
-	gpio_set(GPIO(68), state == CS_DEASSERT);
+	gpio_set(QSPI_CS, state == CS_DEASSERT);
 }
 
 static void configure_gpios(void)
 {
-	gpio_output(GPIO(68), 1);
+	gpio_output(QSPI_CS, 1);
 
-	gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0,
+	gpio_configure(QSPI_DATA_0, GPIO_FUNC_QSPI_DATA_0,
 		GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT);
 
-	gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1,
+	gpio_configure(QSPI_DATA_1, GPIO_FUNC_QSPI_DATA_1,
 		GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT);
 
-	gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK,
+	gpio_configure(QSPI_CLK, GPIO_FUNC_QSPI_CLK,
 		GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT);
 }
 
@@ -240,12 +240,12 @@ static void reg_init(void)
 		(DMA_ENABLE) |
 		(FULL_CYCLE_MODE);
 
-	write32(&sc7180_qspi->mstr_cfg, mstr_config);
-	write32(&sc7180_qspi->ahb_mstr_cfg, 0xA42);
-	write32(&sc7180_qspi->mstr_int_en, 0x0);
-	write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF);
-	write32(&sc7180_qspi->rd_fifo_cfg, 0x0);
-	write32(&sc7180_qspi->rd_fifo_rst, RESET_FIFO);
+	write32(&qcom_qspi->mstr_cfg, mstr_config);
+	write32(&qcom_qspi->ahb_mstr_cfg, 0xA42);
+	write32(&qcom_qspi->mstr_int_en, 0x0);
+	write32(&qcom_qspi->mstr_int_sts, 0xFFFFFFFF);
+	write32(&qcom_qspi->rd_fifo_cfg, 0x0);
+	write32(&qcom_qspi->rd_fifo_rst, RESET_FIFO);
 }
 
 void quadspi_init(uint32_t hz)
@@ -256,13 +256,13 @@ void quadspi_init(uint32_t hz)
 	reg_init();
 }
 
-int sc7180_claim_bus(const struct spi_slave *slave)
+int qspi_claim_bus(const struct spi_slave *slave)
 {
 	cs_change(CS_ASSERT);
 	return 0;
 }
 
-void sc7180_release_bus(const struct spi_slave *slave)
+void qspi_release_bus(const struct spi_slave *slave)
 {
 	cs_change(CS_DEASSERT);
 }
@@ -283,13 +283,13 @@ static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes,
 	return 0;
 }
 
-int sc7180_xfer(const struct spi_slave *slave, const void *dout,
+int qspi_xfer(const struct spi_slave *slave, const void *dout,
 		size_t out_bytes, void *din, size_t in_bytes)
 {
 	return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes);
 }
 
-int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout,
+int qspi_xfer_dual(const struct spi_slave *slave, const void *dout,
 		     size_t out_bytes, void *din, size_t in_bytes)
 {
 	return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes);

src/soc/qualcomm/common/spi.c

@@ -2,35 +2,22 @@
 
 #include <spi-generic.h>
 #include <spi_flash.h>
-#include <soc/qspi.h>
-#include <soc/qupv3_spi.h>
+#include <soc/qspi_common.h>
 
 static const struct spi_ctrlr qspi_ctrlr = {
-	.claim_bus = sc7180_claim_bus,
-	.release_bus = sc7180_release_bus,
-	.xfer = sc7180_xfer,
-	.xfer_dual = sc7180_xfer_dual,
+	.claim_bus = qspi_claim_bus,
+	.release_bus = qspi_release_bus,
+	.xfer = qspi_xfer,
+	.xfer_dual = qspi_xfer_dual,
 	.max_xfer_size = QSPI_MAX_PACKET_COUNT,
 };
 
-const struct spi_ctrlr spi_qup_ctrlr = {
-	.claim_bus = qup_spi_claim_bus,
-	.release_bus = qup_spi_release_bus,
-	.xfer = qup_spi_xfer,
-	.max_xfer_size = 65535,
-};
-
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{
 		.ctrlr = &qspi_ctrlr,
 		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
 		.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
 	},
-	{
-		.ctrlr = &spi_qup_ctrlr,
-		.bus_start = 0,
-		.bus_end = 11,
-	},
 };
 
 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

src/soc/qualcomm/sc7180/Makefile.inc

@@ -5,12 +5,12 @@ decompressor-y += decompressor.c
 decompressor-y += mmu.c
 decompressor-y += ../common/timer.c
 all-y += ../common/timer.c
-all-y += spi.c
 all-y += ../common/gpio.c
+all-y += ../common/spi.c
+all-$(CONFIG_SC7180_QSPI) += ../common/qspi.c
 all-y += qupv3_i2c.c
 all-y += qupv3_spi.c
 all-y += clock.c
-all-$(CONFIG_SC7180_QSPI) += qspi.c
 all-y += ../common/clock.c
 all-y += qcom_qup_se.c
 all-y += qupv3_config.c

src/soc/qualcomm/sc7180/bootblock.c

@@ -2,7 +2,7 @@
 
 #include <bootblock_common.h>
 #include <soc/clock.h>
-#include <soc/qspi.h>
+#include <soc/qspi_common.h>
 #include <soc/qupv3_config.h>
 
 void bootblock_soc_init(void)

src/soc/qualcomm/sc7180/include/soc/addressmap.h

@@ -46,4 +46,14 @@
 #define QMP_PHY_PCS_REG_BASE		0x088e9c00
 #define USB_HOST_DWC3_BASE		0x0a60c100
 
+/* SC7180 QSPI GPIO PINS */
+#define QSPI_CLK			GPIO(63)
+#define QSPI_DATA_0			GPIO(64)
+#define QSPI_DATA_1			GPIO(65)
+#define QSPI_CS				GPIO(68)
+
+#define GPIO_FUNC_QSPI_DATA_0		GPIO64_FUNC_QSPI_DATA_0
+#define GPIO_FUNC_QSPI_DATA_1		GPIO65_FUNC_QSPI_DATA_1
+#define GPIO_FUNC_QSPI_CLK		GPIO63_FUNC_QSPI_CLK
+
 #endif /*  __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */