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icelake: remove unused processor power limits configuration 

Remove unused processor power limit configuration parameter
and function call based on common code base support for
Intel Icelake SoC based platform.

BRANCH=None
BUG=None
TEST=Built for icelake based dragonegg board.

Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41236
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sumeet R Pawnikar 2020-05-08 21:01:31 +05:30 committed by Patrick Georgi
parent b7911c8e98
commit 425d8640fa
2 changed files with 0 additions and 5 deletions
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2
src/soc/intel/icelake/chip.h
View File

@ -171,8 +171,6 @@ struct soc_intel_icelake_config {
/* HeciEnabled decides the state of Heci1 at end of boot /* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */ * Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled; uint8_t HeciEnabled;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
/* Intel Speed Shift Technology */ /* Intel Speed Shift Technology */
uint8_t speed_shift_enable; uint8_t speed_shift_enable;
/* Enable VR specific mailbox command /* Enable VR specific mailbox command

3
src/soc/intel/icelake/include/soc/cpu.h
View File

@ -30,7 +30,4 @@
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10)) (IRTL_1024_NS >> 10))
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
#endif #endif