serial supprt.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -28,6 +28,7 @@ void udelay(int usecs) {
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#define MAXIMUM_CONSOLE_LOGLEVEL 9
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#define DEFAULT_CONSOLE_LOGLEVEL 9
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#include "southbridge/via/vt8231/vt8231_early_serial.c"
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static void memreset_setup(void)
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{
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}
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@ -53,6 +54,7 @@ static void main(void)
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{
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/* init_timer();*/
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enable_vt8231_serial();
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uart_init();
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console_init();
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@ -0,0 +1,71 @@
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/*
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* Enable the serial evices on the VIA
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*/
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/* The base address is 0x15c, 0x2e, depending on config bytes */
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#define SIO_BASE 0x3f0
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#define SIO_DATA SIO_BASE+1
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static void
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vt8231_writesuper(uint8_t reg, uint8_t val) {
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outb(reg, SIO_BASE);
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outb(val, SIO_DATA);
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}
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static void
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vt8231_writesiobyte(uint16_t reg, uint8_t val) {
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outb(val, reg);
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}
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static void
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vt8231_writesioword(uint16_t reg, uint16_t val) {
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outw(val, reg);
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}
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/* regs we use: 85, and the southbridge devfn is defined by the
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mainboard
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*/
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static void
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enable_vt8231_serial(void) {
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device_t dev;
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dev = pci_locate_device(PCI_ID(0x1106,0x3065), 0);
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if (dev == PCI_DEV_INVALID) {
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die("Serial controller not found\r\n");
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}
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/* first, you have to enable the superio and superio config.
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put a 3 in devfn 38 reg 85
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*/
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pci_write_config8(dev, 0x85, 3);
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// now go ahead and set up com1.
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// set address
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vt8231_writesuper(0xf4, 0xfe);
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// enable serial out
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vt8231_writesuper(0xf2, 7);
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// That's it for the sio stuff.
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// movl $SUPERIOCONFIG, %eax
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// movb $9, %dl
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// PCI_WRITE_CONFIG_BYTE
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// set up reg to set baud rate.
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vt8231_writesiobyte(0x3fb, 0x80);
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// Set 115 kb
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vt8231_writesioword(0x3f8, 1);
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// Set 9.6 kb
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// WRITESIOWORD(0x3f8, 12)
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// now set no parity, one stop, 8 bits
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vt8231_writesiobyte(0x3fb, 3);
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// now turn on RTS, DRT
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vt8231_writesiobyte(0x3fc, 3);
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// Enable interrupts
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vt8231_writesiobyte(0x3f9, 0xf);
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// should be done. Dump a char for fun.
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vt8231_writesiobyte(0x3f8, 48);
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}
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