mb/google/nissa: Lock PLT_RST_L pin

There is a requirement that the TPM RST signal cannot be asserted by
software. On nissa this is PLT_RST_L, so lock this pin to prevent it
being reconfigured as a GPIO.

BUG=b:216671701
TEST=Try to change GPP_B13 from the kernel:
$ echo 677 > /sys/class/gpio/export
$ echo out > /sys/class/gpio/gpio677/direction
$ echo 0 > /sys/class/gpio/gpio677/value
$ echo 1 > /sys/class/gpio/gpio677/value
GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED"

Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Reka Norman 2022-07-01 11:14:43 +10:00 committed by Felix Held
parent 5d9b8a9632
commit 42dae32e6c
1 changed files with 1 additions and 1 deletions

View File

@ -78,7 +78,7 @@ static const struct pad_config gpio_table[] = {
/* B12 : SLP_S0# ==> SLP_S0_L */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* B13 : PLTRST# ==> PLT_RST_L */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
/* B14 : SPKR ==> GPP_B14_STRAP */
PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
/* B15 : NC */