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soc/intel/skylake: Don't allow user to change DCACHE base and size 

Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Arthur Heymans 2017-06-13 14:17:05 +02:00 committed by Martin Roth
parent 24c3fef31b
commit 432ac615d0
1 changed files with 2 additions and 2 deletions
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src/soc/intel/skylake/Kconfig
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@ -127,11 +127,11 @@ config CPU_ADDR_BITS
default 36 default 36
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM" hex
default 0xfef00000 default 0xfef00000
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM" hex
default 0x40000 default 0x40000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock