soc/intel/skylake: Don't allow user to change DCACHE base and size
Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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@ -127,11 +127,11 @@ config CPU_ADDR_BITS
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default 36
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config DCACHE_RAM_BASE
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hex "Base address of cache-as-RAM"
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex "Length in bytes of cache-as-RAM"
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hex
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default 0x40000
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help
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The size of the cache-as-ram region required during bootblock
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