Eliminate special case id.inc/id.lds in favor of a configuration variable ID_SECTION_OFFSET
which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative) where necessary (if romstraps get in the way). For Kconfig, the special case is set per southbridge (as these define the necessity for this workaround), for newconfig it's added to each single board. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
c58290c2ff
commit
436f99b72a
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@ -467,3 +467,7 @@ config ENABLE_APIC_EXT_ID
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config WARNINGS_ARE_ERRORS
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bool
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default n
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config ID_SECTION_OFFSET
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hex
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default 0x10
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@ -6,8 +6,8 @@ vendor:
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.asciz CONFIG_MAINBOARD_VENDOR
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part:
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.asciz CONFIG_MAINBOARD_PART_NUMBER
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.long __id_end + 0x10 - vendor /* Reverse offset to the vendor id */
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.long __id_end + 0x10 - part /* Reverse offset to the part number */
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.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
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.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
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.long CONFIG_ROM_SIZE /* Size of this romimage */
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.globl __id_end
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@ -1,5 +1,5 @@
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SECTIONS {
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. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
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. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start);
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.id (.): {
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*(.id)
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}
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@ -1132,3 +1132,8 @@ define CONFIG_PCIE_CONFIGSPACE_HOLE
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comment "Leave a hole for PCIe config space in the device allocator"
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end
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define CONFIG_ID_SECTION_OFFSET
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default 0x10
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export always
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comment "Offset of the .id section. Only needs to change if something like a romstrap is in the way"
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end
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@ -39,7 +39,7 @@ initobj-y += crt0.o
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/southbridge/nvidia/ck804/id.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/southbridge/nvidia/ck804/romstrap.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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@ -47,7 +47,7 @@ crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/southbridge/nvidia/ck804/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/southbridge/nvidia/ck804/romstrap.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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@ -113,6 +113,8 @@ uses CONFIG_AMDMCT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_AMD_UCODE_PATCH_FILE
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uses CONFIG_ID_SECTION_OFFSET
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###
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### Build options
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###
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@ -357,5 +359,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
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## Select power on after power fail setting
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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default CONFIG_ID_SECTION_OFFSET=0x80
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### End Options.lb
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end
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@ -78,8 +78,8 @@ else
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end
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end
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# Include an ID string (for safe flashing).
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mainboardinit southbridge/nvidia/ck804/id.inc
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ldscript /southbridge/nvidia/ck804/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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# ROMSTRAP table for CK804.
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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@ -94,6 +94,7 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
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uses CONFIG_SB_HT_CHAIN_ON_BUS0
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uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_ID_SECTION_OFFSET
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default CONFIG_ROM_SIZE = 512 * 1024
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default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
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@ -162,5 +163,6 @@ default CONFIG_TTYS0_LCS = 0x3
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
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default CONFIG_ID_SECTION_OFFSET = 0x80
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end
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@ -113,8 +113,8 @@ end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit southbridge/sis/sis966/id.inc
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ldscript /southbridge/sis/sis966/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## ROMSTRAP table for MCP55
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@ -33,14 +33,14 @@ initobj-y += crt0.o
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/southbridge/sis/sis966/id.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/southbridge/sis/sis966/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
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@ -115,6 +115,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_ID_SECTION_OFFSET
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###
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### Build options
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###
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@ -347,5 +349,6 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
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## Select power on after power fail setting
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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default CONFIG_ID_SECTION_OFFSET=0x80
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### End Options.lb
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end
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@ -111,8 +111,8 @@ end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit southbridge/nvidia/mcp55/id.inc
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ldscript /southbridge/nvidia/mcp55/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## ROMSTRAP table for MCP55
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@ -36,7 +36,7 @@ initobj-y += crt0.o
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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@ -44,7 +44,7 @@ crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
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@ -116,6 +116,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
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uses CONFIG_ID_SECTION_OFFSET
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###
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### Build options
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###
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@ -356,5 +358,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
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## Select power on after power fail setting
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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default CONFIG_ID_SECTION_OFFSET=0x80
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### End Options.lb
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end
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@ -107,8 +107,8 @@ end
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##
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## Include an ID string (for safe flashing).
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##
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mainboardinit southbridge/nvidia/ck804/id.inc
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ldscript /southbridge/nvidia/ck804/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## ROMSTRAP table for CK804
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@ -99,6 +99,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
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uses CONFIG_SB_HT_CHAIN_ON_BUS0
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uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
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uses CONFIG_ID_SECTION_OFFSET
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## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
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## ---> 512 Kbytes
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default CONFIG_ROM_SIZE=(512*1024)
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## Select power on after power fail setting
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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default CONFIG_ID_SECTION_OFFSET=0x80
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### End Options.lb
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end
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@ -93,8 +93,8 @@ else
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end
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end
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mainboardinit southbridge/nvidia/mcp55/id.inc
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ldscript /southbridge/nvidia/mcp55/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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# ROMSTRAP table for MCP55.
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if CONFIG_HAVE_FAILOVER_BOOT
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@ -33,14 +33,14 @@ initobj-y += crt0.o
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
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@ -96,6 +96,7 @@ uses CONFIG_AP_CODE_IN_CAR
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uses CONFIG_MEM_TRAIN_SEQ
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uses CONFIG_WAIT_BEFORE_CPUS_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_ID_SECTION_OFFSET
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default CONFIG_ROM_SIZE = 512 * 1024
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default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
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@ -182,5 +183,6 @@ default CONFIG_TTYS0_LCS = 0x3
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
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default CONFIG_ID_SECTION_OFFSET=0x80
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end
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@ -94,8 +94,8 @@ end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit southbridge/nvidia/mcp55/id.inc
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ldscript /southbridge/nvidia/mcp55/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## ROMSTRAP table for MCP55
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@ -35,14 +35,14 @@ initobj-y += crt0.o
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
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@ -99,6 +99,8 @@ uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_ID_SECTION_OFFSET
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## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
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#512K bytes
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default CONFIG_ROM_SIZE=524288
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@ -303,5 +305,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
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## Select power on after power fail setting
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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default CONFIG_ID_SECTION_OFFSET=0x80
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### End Options.lb
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end
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@ -141,8 +141,8 @@ end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit southbridge/nvidia/mcp55/id.inc
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ldscript /southbridge/nvidia/mcp55/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## ROMSTRAP table for MCP55
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@ -33,7 +33,7 @@ initobj-y += crt0.o
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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@ -41,7 +41,7 @@ crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
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@ -113,6 +113,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
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|||
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||||
uses CONFIG_USE_PRINTK_IN_CAR
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||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
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||||
|
||||
###
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||||
### Build options
|
||||
###
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||||
|
@ -345,5 +347,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
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## Select power on after power fail setting
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default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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||||
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||||
default CONFIG_ID_SECTION_OFFSET=0x80
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||||
### End Options.lb
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||||
end
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||||
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@ -62,8 +62,8 @@ end
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|||
##
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||||
## Include an id string (For safe flashing)
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||||
##
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||||
mainboardinit southbridge/nvidia/ck804/id.inc
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||||
ldscript /southbridge/nvidia/ck804/id.lds
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## ROMSTRAP table for CK804
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@ -69,6 +69,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
|||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
#512K bytes
|
||||
#default CONFIG_ROM_SIZE=524288
|
||||
|
@ -272,5 +274,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
|||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -108,8 +108,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/mcp55/id.inc
|
||||
ldscript /southbridge/nvidia/mcp55/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for MCP55
|
||||
|
|
|
@ -34,7 +34,7 @@ initobj-y += crt0.o
|
|||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
@ -42,7 +42,7 @@ crt0-y += auto.inc
|
|||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
|
|
|
@ -114,6 +114,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
|||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
@ -347,5 +349,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
|
|||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -110,8 +110,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/mcp55/id.inc
|
||||
ldscript /southbridge/nvidia/mcp55/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for MCP55
|
||||
|
|
|
@ -33,7 +33,7 @@ initobj-y += crt0.o
|
|||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
@ -41,7 +41,7 @@ crt0-y += auto.inc
|
|||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
|
|
|
@ -112,6 +112,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
|||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
@ -345,5 +347,7 @@ default CONFIG_USE_FAILOVER_IMAGE=0
|
|||
default CONFIG_USE_FALLBACK_IMAGE=0
|
||||
default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -112,8 +112,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/mcp55/id.inc
|
||||
ldscript /southbridge/nvidia/mcp55/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for MCP55
|
||||
|
|
|
@ -33,7 +33,7 @@ initobj-y += crt0.o
|
|||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
@ -41,7 +41,7 @@ crt0-y += auto.inc
|
|||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
|
|
|
@ -115,6 +115,7 @@ uses CONFIG_AMDMCT
|
|||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_AMD_UCODE_PATCH_FILE
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
###
|
||||
### Build options
|
||||
|
@ -356,5 +357,7 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
|||
default CONFIG_USE_FAILOVER_IMAGE=0
|
||||
default CONFIG_USE_FALLBACK_IMAGE=0
|
||||
default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -77,8 +77,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/ck804/id.inc
|
||||
ldscript /southbridge/nvidia/ck804/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for CK804
|
||||
|
|
|
@ -77,6 +77,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
|||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE=512*1024
|
||||
|
||||
|
@ -294,5 +296,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
|||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -78,8 +78,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/ck804/id.inc
|
||||
ldscript /southbridge/nvidia/ck804/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for CK804
|
||||
|
|
|
@ -71,6 +71,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
|||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE=1024*1024
|
||||
|
||||
|
@ -282,5 +284,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
|||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -90,8 +90,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/ck804/id.inc
|
||||
ldscript /southbridge/nvidia/ck804/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for CK804
|
||||
|
|
|
@ -82,6 +82,8 @@ uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
|||
|
||||
uses CONFIG_RAMTOP
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE=1024*1024
|
||||
|
||||
|
@ -303,5 +305,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
|||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -111,8 +111,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/mcp55/id.inc
|
||||
ldscript /southbridge/nvidia/mcp55/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for MCP55
|
||||
|
|
|
@ -33,7 +33,7 @@ initobj-y += crt0.o
|
|||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
@ -41,7 +41,7 @@ crt0-y += auto.inc
|
|||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
|
||||
|
|
|
@ -113,6 +113,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
|||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
@ -347,5 +349,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
|||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -111,8 +111,8 @@ end
|
|||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit southbridge/nvidia/mcp55/id.inc
|
||||
ldscript /southbridge/nvidia/mcp55/id.lds
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for MCP55
|
||||
|
|
|
@ -33,7 +33,7 @@ initobj-y += crt0.o
|
|||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
@ -41,7 +41,7 @@ crt0-y += auto.inc
|
|||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
|
||||
|
|
|
@ -115,6 +115,7 @@ uses CONFIG_AMDMCT
|
|||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_AMD_UCODE_PATCH_FILE
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
###
|
||||
### Build options
|
||||
|
@ -355,5 +356,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
|||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
|
@ -3,3 +3,7 @@ config SOUTHBRIDGE_NVIDIA_CK804
|
|||
select HAVE_HARD_RESET
|
||||
select IOAPIC
|
||||
|
||||
config ID_SECTION_OFFSET
|
||||
hex
|
||||
default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
|
||||
|
||||
|
|
|
@ -1,15 +0,0 @@
|
|||
.section ".id", "a", @progbits
|
||||
|
||||
.globl __id_start
|
||||
__id_start:
|
||||
vendor:
|
||||
.asciz CONFIG_MAINBOARD_VENDOR
|
||||
part:
|
||||
.asciz CONFIG_MAINBOARD_PART_NUMBER
|
||||
.long __id_end + 0x80 - vendor /* Reverse offset to the vendor ID */
|
||||
.long __id_end + 0x80 - part /* Reverse offset to the part number */
|
||||
.long CONFIG_ROM_SIZE /* Size of this ROM image */
|
||||
.globl __id_end
|
||||
|
||||
__id_end:
|
||||
.previous
|
|
@ -1,6 +0,0 @@
|
|||
SECTIONS {
|
||||
. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
|
||||
.id (.): {
|
||||
*(.id)
|
||||
}
|
||||
}
|
|
@ -1,2 +1,6 @@
|
|||
config SOUTHBRIDGE_NVIDIA_MCP55
|
||||
bool
|
||||
|
||||
config ID_SECTION_OFFSET
|
||||
hex
|
||||
default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
|
||||
|
|
|
@ -1,36 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
.section ".id", "a", @progbits
|
||||
|
||||
.globl __id_start
|
||||
__id_start:
|
||||
vendor:
|
||||
.asciz CONFIG_MAINBOARD_VENDOR
|
||||
part:
|
||||
.asciz CONFIG_MAINBOARD_PART_NUMBER
|
||||
.long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */
|
||||
.long __id_end + 0x80 - part /* Reverse offset to the part number */
|
||||
.long CONFIG_ROM_SIZE /* Size of this romimage */
|
||||
.globl __id_end
|
||||
|
||||
__id_end:
|
||||
.previous
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
SECTIONS {
|
||||
. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
|
||||
.id (.): {
|
||||
*(.id)
|
||||
}
|
||||
}
|
|
@ -1,2 +1,6 @@
|
|||
config SOUTHBRIDGE_SIS_SIS966
|
||||
bool
|
||||
|
||||
config ID_SECTION_OFFSET
|
||||
hex
|
||||
default 0x80 if SOUTHBRIDGE_SIS_SIS966
|
||||
|
|
|
@ -1,36 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
.section ".id", "a", @progbits
|
||||
|
||||
.globl __id_start
|
||||
__id_start:
|
||||
vendor:
|
||||
.asciz CONFIG_MAINBOARD_VENDOR
|
||||
part:
|
||||
.asciz CONFIG_MAINBOARD_PART_NUMBER
|
||||
.long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */
|
||||
.long __id_end + 0x80 - part /* Reverse offset to the part number */
|
||||
.long CONFIG_ROM_SIZE /* Size of this romimage */
|
||||
.globl __id_end
|
||||
|
||||
__id_end:
|
||||
.previous
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
SECTIONS {
|
||||
. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
|
||||
.id (.): {
|
||||
*(.id)
|
||||
}
|
||||
}
|
Loading…
Reference in New Issue