GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/sarien: Enable DMI/SATA power Optimize 

Turn on power optimizer of PCH side DMI and SATA controller.

BUG=N/A
TEST=Build and boot up into sarien platoform, able to finish 100 cycles
of s0ix.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I41da2b4106d683945cdc296e2a77311176144f43
Reviewed-on: https://review.coreboot.org/c/30212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Lijian Zhao 2018-12-13 09:26:39 -08:00 committed by Patrick Georgi
parent 9bf1d8f276
commit 43825e8960
2 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -27,6 +27,8 @@ chip soc/intel/cannonlake
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -31,6 +31,8 @@ chip soc/intel/cannonlake
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port