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mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references 

Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Martin Roth 2017-06-24 21:54:33 -06:00
parent 356b519049
commit 43927bae18
40 changed files with 81 additions and 81 deletions
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6
src/mainboard/msi/ms7135/romstage.c
View File

@ -41,7 +41,7 @@
#include <spd.h>
#include <northbridge/amd/amdk8/pre_f.h>
#if CONFIG_HAVE_OPTION_TABLE
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ms7135_set_nf4_voltage();
ms7135_set_ram_voltage();
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
dump_spd_registers(&ctrl[0]);
dump_smbus_registers();
#endif

4
src/mainboard/msi/ms7260/romstage.c
View File

@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched
* becase optimize_link_coherent_ht is moved out from
* setup_coherent_ht_domain, so here need to make sure last core0 is
@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);

2
src/mainboard/msi/ms7721/buildOpts.c
View File

@ -168,7 +168,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/

2
src/mainboard/msi/ms9185/mptable.c
View File

@ -26,7 +26,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>

4
src/mainboard/msi/ms9185/romstage.c
View File

@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

2
src/mainboard/msi/ms9282/romstage.c
View File

@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
start_other_cores();
//wait_all_other_cores_started(bsp_apicid);

4
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -189,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

4
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

2
src/mainboard/samsung/lumpy/acpi_tables.c
View File

@ -25,7 +25,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <ec/acpi/ec.h>
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif

4
src/mainboard/samsung/lumpy/romstage.c
View File

@ -38,7 +38,7 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include "option_table.h"
#if CONFIG_DRIVERS_UART_8250IO
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
@ -47,7 +47,7 @@ void pch_enable_lpc(void)
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
#if CONFIG_DRIVERS_UART_8250IO
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
/* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);

6
src/mainboard/samsung/stumpy/romstage.c
View File

@ -38,12 +38,12 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include <tpm.h>
#if CONFIG_DRIVERS_UART_8250IO
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
/* Stumpy USB Reset Disable defined in cmos.layout */
#if CONFIG_USE_OPTION_TABLE
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
#include "option_table.h"
#define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3)
#else
@ -60,7 +60,7 @@ void pch_enable_lpc(void)
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
#if CONFIG_DRIVERS_UART_8250IO
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
/* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
CNF2_LPC_EN | COMA_LPC_EN);

2
src/mainboard/siemens/mc_bdx1/mainboard.c
View File

@ -22,7 +22,7 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>

2
src/mainboard/siemens/mc_tcu3/mainboard.c
View File

@ -21,7 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>

2
src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
View File

@ -65,7 +65,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
IO_APIC_ADDR, 0);
#if !CONFIG_LINT01_CONVERSION
#if !IS_ENABLED(CONFIG_LINT01_CONVERSION)
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);

10
src/mainboard/siemens/sitemp_g1p1/mainboard.c
View File

@ -30,7 +30,7 @@
#include <southbridge/amd/rs690/chip.h>
#include <southbridge/amd/rs690/rs690.h>
#include <superio/ite/it8712f/it8712f.h>
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#include <x86emu/x86emu.h>
#endif
#include "int15_func.h"
@ -215,7 +215,7 @@ struct fan_control {
u8 t_range;
};
/* ############################################################################################# */
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
static int int15_handler(void)
{
#define BOOT_DISPLAY_DEFAULT 0
@ -779,14 +779,14 @@ void smm_lock(void)
static void mainboard_init(device_t dev)
{
#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
INT15_function_extensions int15_func;
#endif
printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
if (get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") != CB_SUCCESS)
int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
int15_func.regs.func05_TV_standard = TV_MODE_NO;
@ -808,7 +808,7 @@ static void mainboard_enable(device_t dev)
printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif

2
src/mainboard/siemens/sitemp_g1p1/romstage.c
View File

@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

2
src/mainboard/sunw/ultra40/romstage.c
View File

@ -124,7 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

4
src/mainboard/sunw/ultra40m2/romstage.c
View File

@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

6
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -154,13 +154,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
dump_smbus_registers();
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

4
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

4
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);

4
src/mainboard/supermicro/h8qgi/buildOpts.c
View File

@ -426,10 +426,10 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
*/
/*
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#endif
*/

4
src/mainboard/supermicro/h8qgi/rd890_cfg.h
View File

@ -27,10 +27,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif

8
src/mainboard/supermicro/h8qgi/sb700_cfg.h
View File

@ -36,13 +36,13 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
#define BIOS_SIZE BIOS_SIZE_2M
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
#define BIOS_SIZE BIOS_SIZE_4M
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
#define BIOS_SIZE BIOS_SIZE_8M
#endif
#endif

4
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -239,7 +239,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

4
src/mainboard/supermicro/h8scm/rd890_cfg.h
View File

@ -27,10 +27,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif

8
src/mainboard/supermicro/h8scm/sb700_cfg.h
View File

@ -36,13 +36,13 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
#define BIOS_SIZE BIOS_SIZE_2M
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
#define BIOS_SIZE BIOS_SIZE_4M
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
#define BIOS_SIZE BIOS_SIZE_8M
#endif
#endif

4
src/mainboard/supermicro/h8scm_fam10/romstage.c
View File

@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sr5650_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

6
src/mainboard/technexion/tim5690/mainboard.c
View File

@ -184,7 +184,7 @@ static void mb_gpio_init(u16 *iobase)
it8712f_exit_conf();
}
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
/* The LCD's panel id seletion. */
static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
{
@ -221,7 +221,7 @@ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
static void mainboard_enable(device_t dev)
{
u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
rs690_vbios_regs vbios_regs;
u8 port2;
#endif
@ -230,7 +230,7 @@ static void mainboard_enable(device_t dev)
mb_gpio_init(&gpio_base);
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
/* The LCD's panel id seletion by switch. */
port2 = inb(gpio_base+1);
lcd_panel_id(&vbios_regs, ((~port2) & 0xf));

2
src/mainboard/technexion/tim5690/romstage.c
View File

@ -95,7 +95,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

2
src/mainboard/technexion/tim8690/romstage.c
View File

@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

4
src/mainboard/thomson/ip1000/spd_table.h
View File

@ -16,11 +16,11 @@
#include <spd.h>
#if CONFIG_ONBOARD_MEMORY_64MB
#if IS_ENABLED(CONFIG_ONBOARD_MEMORY_64MB)
#define DENSITY 0x10
#elif CONFIG_ONBOARD_MEMORY_128MB
#elif IS_ENABLED(CONFIG_ONBOARD_MEMORY_128MB)
#define DENSITY 0x20

4
src/mainboard/tyan/s2912/romstage.c
View File

@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

4
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -184,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

4
src/mainboard/tyan/s8226/buildOpts.c
View File

@ -426,10 +426,10 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
*/
/*
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#endif
*/

4
src/mainboard/tyan/s8226/rd890_cfg.h
View File

@ -27,10 +27,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif

8
src/mainboard/tyan/s8226/sb700_cfg.h
View File

@ -36,13 +36,13 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
#define BIOS_SIZE BIOS_SIZE_2M
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
#define BIOS_SIZE BIOS_SIZE_4M
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
#define BIOS_SIZE BIOS_SIZE_8M
#endif
#endif

4
src/mainboard/via/epia-m850/mainboard.c
View File

@ -19,7 +19,7 @@
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <arch/interrupt.h>
#include <x86emu/x86emu.h>
@ -96,7 +96,7 @@ static void mainboard_enable(device_t dev)
{
(void)dev;
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
printk(BIOS_DEBUG, "Installing INT15 handler...\n");
mainboard_interrupt_handlers(0x15, &vx900_int15_handler);
#endif

2
src/mainboard/via/epia-m850/romstage.c
View File

@ -90,7 +90,7 @@ void main(unsigned long bist)
printk(BIOS_DEBUG, "We passed RAM verify\n");
/* We got RAM working, now we can write the timestamps to RAM */
#if CONFIG_EARLY_CBMEM_INIT
#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
cbmem_recovery(0);
#endif
/* FIXME: See if this is needed or take this out please */

4
src/mainboard/winent/mb6047/romstage.c
View File

@ -37,7 +37,7 @@ int spd_read_byte(unsigned device, unsigned address)
#include <southbridge/nvidia/ck804/early_setup_ss.h>
#include "southbridge/nvidia/ck804/early_setup_car.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "northbridge/amd/amdk8/early_ht.c"
@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
if ((cpuid_edx(0x80000007) & 0x6) == 0x6) {