mb/google/sarien: Disable S5 wake on LAN by default

Chromebook doesn't require support wake on LAN in S5.
Disable it by default for power saving.

BUG=b:131571666
TEST= check LAN indicator is off under S5

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -53,6 +53,9 @@ chip soc/intel/cannonlake
 	# Enable DDC for DDI port B
 	register "DdiPortBDdc" = "1"
 
+	register "LanWakeFromDeepSx" = "0"
+	register "WolEnableOverride" = "0"
+
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
 	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |

src/soc/intel/cannonlake/chip.h

@@ -400,6 +400,10 @@ struct soc_intel_cannonlake_config {
 
 	/* Unlock all GPIO Pads */
 	uint8_t PchUnlockGpioPads;
+
+	/* Enable GBE wakeup */
+	uint8_t LanWakeFromDeepSx;
+	uint8_t WolEnableOverride;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/fsp_params.c

@@ -212,6 +212,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->DdiPortDDdc = config->DdiPortDDdc;
 	params->DdiPortFDdc = config->DdiPortFDdc;
 
+	/* WOL */
+	params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
+	params->PchPmWolEnableOverride = config->WolEnableOverride;
+
 	/* S0ix */
 	params->PchPmSlpS0Enable = config->s0ix_enable;