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glados: enable SMBus device 

In order to run with the debug FSP the SMBus device needs
to be enabled. Additionally, the TCO block lives within
the SMBus device so if TCO is to be employed then the
SMBus device needs to be enabled as a prerequisite.

BUG=chrome-os-partner:42407
BRANCH=None
TEST=Buit and booted into kernel.

Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290364
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>

Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11181
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2015-08-04 11:03:00 -05:00
parent a7a57701d6
commit 43b1066c0d
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/glados/devicetree.cb
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@ -44,7 +44,7 @@ chip soc/intel/skylake
register "IshEnable" = "0"
register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -102,7 +102,7 @@ chip soc/intel/skylake
end # LPC Interface
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel High Definition Audio
device pci 1f.4 off end # SMBus Controller
device pci 1f.4 on end # SMBus Controller
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE Controller
end