[REMOVAL] ibm/e325 + ibm/e326
As announced in http://permalink.gmane.org/gmane.linux.bios/81918 I am removing all boards older than 10 years from the tree. Change-Id: I8854c31f242c13b6f91901452f7eb7ce0ef0b255 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12370 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Stefan Reinauer
parent
7804bb002f
commit
43f6fd3827
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@ -1,16 +0,0 @@
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if VENDOR_IBM
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choice
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prompt "Mainboard model"
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source "src/mainboard/ibm/*/Kconfig.name"
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endchoice
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source "src/mainboard/ibm/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "IBM"
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endif # VENDOR_IBM
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@ -1,2 +0,0 @@
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config VENDOR_IBM
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bool "IBM"
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@ -1,58 +0,0 @@
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if BOARD_IBM_E325
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_SOCKET_940
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_AMD_AMD8111
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select SOUTHBRIDGE_AMD_AMD8131
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select SUPERIO_NSC_PC87366
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select PARALLEL_CPU_INIT
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select BOARD_ROMSIZE_KB_512
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select QRANK_DIMM_SUPPORT
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config MAINBOARD_DIR
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string
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default ibm/e325
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config DCACHE_RAM_BASE
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hex
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default 0xcf000
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config DCACHE_RAM_SIZE
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hex
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default 0x1000
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "eServer 325"
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config MAX_CPUS
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int
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default 1
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x1
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config IRQ_SLOT_COUNT
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int
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default 12
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endif # BOARD_IBM_E325
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@ -1,2 +0,0 @@
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config BOARD_IBM_E325
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bool "eServer 325"
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@ -1,2 +0,0 @@
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Category: server
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Board URL: http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-53255
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@ -1,60 +0,0 @@
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entries
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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399 1 e 2 multi_core
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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445 1 e 1 iommu
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456 1 e 1 ECC_memory
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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8 0 DDR400
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8 1 DDR333
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8 2 DDR266
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8 3 DDR200
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9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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checksum 392 983 984
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@ -1,69 +0,0 @@
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chip northbridge/amd/amdk8/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/socket_940
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device lapic 0 on end
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end
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end
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device domain 0 on
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chip northbridge/amd/amdk8
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device pci 18.0 on end # LDT 0
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device pci 18.0 on # LDT 1
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chip southbridge/amd/amd8131
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.1 on end
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end
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chip southbridge/amd/amd8111
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device pci 0.0 on
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 on end
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device pci 1.0 off end
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end
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device pci 1.0 on
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chip superio/nsc/pc87366
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 off end # SWC
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device pnp 2e.5 off end # Mouse
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.7 off end # GPIO
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device pnp 2e.8 off end # ACB
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device pnp 2e.9 off end # FSCM
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device pnp 2e.a off end # WDT
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end
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end
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device pci 1.1 on end
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device pci 1.2 on end
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device pci 1.3 on end
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device pci 1.5 off end
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device pci 1.6 off end
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end
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end # device pci 18.0
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device pci 18.0 on end # LDT2
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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end
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@ -1,60 +0,0 @@
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#include <arch/pirq_routing.h>
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#include <device/pci.h>
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#define IRQ_ROUTER_BUS 0
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#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
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#define IRQ_ROUTER_VENDOR 0x1022
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#define IRQ_ROUTER_DEVICE 0x746b
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#define AVAILABLE_IRQS 0xdef8
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#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
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{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
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{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
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/* Each IRQ_SLOT entry consists of:
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* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
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*/
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static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
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IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
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IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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IRQ_ROUTER_VENDOR, /* Vendor */
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IRQ_ROUTER_DEVICE, /* Device */
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0x00, /* Miniport data */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x34, /* u8 checksum , mod 256 checksum must give zero */
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{ /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
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/* Northbridge, Node 0 */
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IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0),
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/* AMD-8131 PCI-X Bridge */
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IRQ_SLOT(0x0, 0x01,0x01,0x0, 0,0,0,0),
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/* Onboard LSI SCSI Controller */
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IRQ_SLOT(0x0, 0x02,0x02,0x0, 3,0,0,0),
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/* Onboard Broadcom NICs */
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IRQ_SLOT(0x0, 0x02,0x01,0x0, 1,2,0,0),
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/* AMD-8131 PCI-X Bridge */
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IRQ_SLOT(0x0, 0x01,0x02,0x0, 0,0,0,0),
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/* PCI Slot 1-2 */
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IRQ_SLOT(0x1, 0x03,0x03,0x0, 1,2,3,4),
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IRQ_SLOT(0x2, 0x03,0x04,0x0, 2,3,4,1),
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/* AMD-8111 PCI Bridge */
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IRQ_SLOT(0x0, 0x01,0x03,0x0, 0,0,0,0),
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/* USB Controller */
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IRQ_SLOT(0x0, 0x04,0x00,0x0, 0,0,0,4),
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/* ATI Rage XL VGA */
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IRQ_SLOT(0x0, 0x04,0x05,0x0, 1,0,0,0),
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/* AMD-8111 LPC Dridge */
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IRQ_SLOT(0x0, 0x01,0x04,0x0, 0,0,0,0),
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/* Northbridge, Node 1 */
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IRQ_SLOT(0x0, 0x00,0x19,0x0, 0,0,0,0),
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr, &intel_irq_routing_table);
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}
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@ -1,133 +0,0 @@
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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unsigned char bus_8111_0;
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unsigned char bus_8111_1;
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unsigned char bus_8131_1;
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unsigned char bus_8131_2;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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{
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device_t dev;
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/* 8111 */
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dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
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if (dev) {
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bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
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bus_8111_0 = 1;
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bus_8111_1 = 4;
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}
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/* 8131-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
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bus_8131_1 = 2;
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}
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/* 8131-2 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_8131_2 = 3;
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}
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}
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mptable_write_buses(mc, NULL, &bus_isa);
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/* Legacy IOAPIC #2 */
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smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
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{
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device_t dev;
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struct resource *res;
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/* 8131-1 apic #3 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x03, 0x11,
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res2mmio(res, 0, 0));
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}
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}
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/* 8131-2 apic #4 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x04, 0x11,
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res2mmio(res, 0, 0));
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}
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}
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}
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mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
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/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
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/* Integrated SMBus 2.0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
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/* Integrated AMD AC97 Audio */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
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/* Integrated AMD USB */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
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/* On board ATI Rage XL */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
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/* On board Broadcom nics */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
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/* On board LSI SCSI */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
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/* PCI Slot 1 PCIX */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
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/* PCI Slot 2 PCIX */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
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/* Standard local interrupt assignments:
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* Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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mptable_lintsrc(mc, bus_isa);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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@ -1,271 +0,0 @@
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/*
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* IBM E325 needs a different resource map
|
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*
|
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*/
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static void setup_ibm_e325_resource_map(void)
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{
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static const unsigned int register_values[] = {
|
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/* Careful set limit registers before base registers which contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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* F1:0x4C i = 1
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* F1:0x54 i = 2
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* F1:0x5C i = 3
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* F1:0x64 i = 4
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* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0,
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33,
|
||||
PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0,
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
|
||||
PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
|
||||
};
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <stdlib.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "southbridge/amd/amd8111/early_smbus.c"
|
||||
#include <northbridge/amd/amdk8/raminit.h>
|
||||
#include <delay.h>
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include <superio/nsc/pc87366/pc87366.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include <spd.h>
|
||||
#include "southbridge/amd/amd8111/early_ctrl.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
/* Set the memreset low. */
|
||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
|
||||
/* Ensure the BIOS has control of the memory lines. */
|
||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
} else {
|
||||
/* Ensure the CPU has control of the memory lines. */
|
||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
/* Set memreset high. */
|
||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static void activate_spd_rom(const struct mem_controller *ctrl) { }
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "resourcemap.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { DIMM0, DIMM2, 0, 0 },
|
||||
.channel1 = { DIMM1, DIMM3, 0, 0 },
|
||||
},
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
{
|
||||
.node_id = 1,
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { DIMM4, DIMM6, 0, 0 },
|
||||
.channel1 = { DIMM5, DIMM7, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
|
||||
if (bist == 0)
|
||||
init_cpus(cpu_init_detectedx);
|
||||
|
||||
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_ibm_e325_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
#endif
|
||||
// automatically set that for you, but you might meet tight space
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
if (needs_reset) {
|
||||
printk(BIOS_INFO, "ht reset -\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(ARRAY_SIZE(cpu), cpu);
|
||||
|
||||
post_cache_as_ram();
|
||||
}
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
if BOARD_IBM_E326
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_940
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_AMD_AMD8111
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select SUPERIO_NSC_PC87366
|
||||
select PARALLEL_CPU_INIT
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select BOARD_ROMSIZE_KB_512
|
||||
select QRANK_DIMM_SUPPORT
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default ibm/e326
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xcf000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x1000
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "eServer 326"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x20
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 12
|
||||
|
||||
endif # BOARD_IBM_E326
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_IBM_E326
|
||||
bool "eServer 326"
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Category: server
|
||||
Board URL: http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-58655
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
8 0 DDR400
|
||||
8 1 DDR333
|
||||
8 2 DDR266
|
||||
8 3 DDR200
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on end # LDT 0
|
||||
device pci 18.0 on # LDT 1
|
||||
chip southbridge/amd/amd8131
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 on end
|
||||
device pci 1.0 off end
|
||||
device pci 5.0 on end # ATI Rage XL
|
||||
end
|
||||
device pci 1.0 on
|
||||
chip superio/nsc/pc87366
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 off # Com 2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Com 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # SWC
|
||||
device pnp 2e.5 off end # Mouse
|
||||
device pnp 2e.6 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # ACB
|
||||
device pnp 2e.9 off end # FSCM
|
||||
device pnp 2e.a off end # WDT
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
device pci 1.3 on end
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
device pci 18.0 on end # LDT2
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
#include <arch/pirq_routing.h>
|
||||
#include <device/pci.h>
|
||||
|
||||
#define IRQ_ROUTER_BUS 0
|
||||
#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
|
||||
#define IRQ_ROUTER_VENDOR 0x1022
|
||||
#define IRQ_ROUTER_DEVICE 0x746b
|
||||
|
||||
#define AVAILABLE_IRQS 0xdef8
|
||||
#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
|
||||
{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
|
||||
{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
|
||||
|
||||
/* Each IRQ_SLOT entry consists of:
|
||||
* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
|
||||
*/
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
|
||||
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
|
||||
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
IRQ_ROUTER_VENDOR, /* Vendor */
|
||||
IRQ_ROUTER_DEVICE, /* Device */
|
||||
0x00, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x34, /* u8 checksum , mod 256 checksum must give zero */
|
||||
{ /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
|
||||
/* Northbridge, Node 0 */
|
||||
IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0),
|
||||
/* AMD-8131 PCI-X Bridge */
|
||||
IRQ_SLOT(0x0, 0x01,0x01,0x0, 0,0,0,0),
|
||||
/* Onboard LSI SCSI Controller */
|
||||
IRQ_SLOT(0x0, 0x02,0x02,0x0, 3,0,0,0),
|
||||
/* Onboard Broadcom NICs */
|
||||
IRQ_SLOT(0x0, 0x02,0x01,0x0, 1,2,0,0),
|
||||
/* AMD-8131 PCI-X Bridge */
|
||||
IRQ_SLOT(0x0, 0x01,0x02,0x0, 0,0,0,0),
|
||||
/* PCI Slot 1-2 */
|
||||
IRQ_SLOT(0x1, 0x03,0x03,0x0, 1,2,3,4),
|
||||
IRQ_SLOT(0x2, 0x03,0x04,0x0, 2,3,4,1),
|
||||
/* AMD-8111 PCI Bridge */
|
||||
IRQ_SLOT(0x0, 0x01,0x03,0x0, 0,0,0,0),
|
||||
/* USB Controller */
|
||||
IRQ_SLOT(0x0, 0x04,0x00,0x0, 0,0,0,4),
|
||||
/* ATI Rage XL VGA */
|
||||
IRQ_SLOT(0x0, 0x04,0x05,0x0, 1,0,0,0),
|
||||
/* AMD-8111 LPC Dridge */
|
||||
IRQ_SLOT(0x0, 0x01,0x04,0x0, 0,0,0,0),
|
||||
/* Northbridge, Node 1 */
|
||||
IRQ_SLOT(0x0, 0x00,0x19,0x0, 0,0,0,0),
|
||||
|
||||
}
|
||||
};
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
|
||||
int bus_isa;
|
||||
unsigned char bus_8111_0;
|
||||
unsigned char bus_8111_1;
|
||||
unsigned char bus_8131_1;
|
||||
unsigned char bus_8131_2;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||
bus_8111_0 = 1;
|
||||
bus_8111_1 = 4;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||
bus_8131_1 = 2;
|
||||
}
|
||||
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
bus_8131_2 = 3;
|
||||
}
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* Legacy IOAPIC #2 */
|
||||
smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
/* 8131-1 apic #3 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x03, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
/* 8131-2 apic #4 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
|
||||
|
||||
/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
|
||||
/* Integrated SMBus 2.0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
|
||||
/* Integrated AMD AC97 Audio */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
|
||||
|
||||
/* Integrated AMD USB */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
|
||||
|
||||
/* On board ATI Rage XL */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
|
||||
|
||||
/* On board Broadcom nics */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
|
||||
|
||||
/* On board LSI SCSI */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
|
||||
|
||||
/* PCI Slot 1 PCIX */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
|
||||
|
||||
/* PCI Slot 2 PCIX */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
|
||||
|
||||
/* Standard local interrupt assignments:
|
||||
* Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,271 +0,0 @@
|
|||
/*
|
||||
* IBM E325 needs a different resource map
|
||||
*
|
||||
*/
|
||||
|
||||
static void setup_ibm_e326_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0,
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33,
|
||||
PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0,
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
|
||||
PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
|
||||
};
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <stdlib.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "southbridge/amd/amd8111/early_smbus.c"
|
||||
#include <northbridge/amd/amdk8/raminit.h>
|
||||
#include <delay.h>
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include <superio/nsc/pc87366/pc87366.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "southbridge/amd/amd8111/early_ctrl.c"
|
||||
#include <spd.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
/* Set the memreset low. */
|
||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
|
||||
/* Ensure the BIOS has control of the memory lines. */
|
||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
} else {
|
||||
/* Ensure the CPU has control of the memory lines. */
|
||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
/* Set memreset high. */
|
||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static void activate_spd_rom(const struct mem_controller *ctrl) { }
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "resourcemap.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { DIMM0, DIMM2, 0, 0 },
|
||||
.channel1 = { DIMM1, DIMM3, 0, 0 },
|
||||
},
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
{
|
||||
.node_id = 1,
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { DIMM4, DIMM6, 0, 0 },
|
||||
.channel1 = { DIMM5, DIMM7, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
|
||||
if (bist == 0)
|
||||
init_cpus(cpu_init_detectedx);
|
||||
|
||||
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_ibm_e326_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
#endif
|
||||
// automatically set that for you, but you might meet tight space
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
if (needs_reset) {
|
||||
printk(BIOS_INFO, "ht reset -\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(ARRAY_SIZE(cpu), cpu);
|
||||
|
||||
post_cache_as_ram();
|
||||
}
|
||||
Loading…
Reference in New Issue