inteltool: Show more info on sandy/ivy.
Change-Id: I408614e743ab6f0f447b327c01d8f4dacf787124 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6692 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko
parent
ab83ef02c7
commit
44bc11c3eb
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@ -27,7 +27,7 @@ PREFIX ?= /usr/local
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CFLAGS ?= -O2 -g -Wall -W
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CFLAGS ?= -O2 -g -Wall -W
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LDFLAGS += -lpci -lz
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LDFLAGS += -lpci -lz
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OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o
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OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o
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OS_ARCH = $(shell uname)
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OS_ARCH = $(shell uname)
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ifeq ($(OS_ARCH), Darwin)
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ifeq ($(OS_ARCH), Darwin)
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@ -193,3 +193,4 @@ int print_epbar(struct pci_dev *nb);
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int print_dmibar(struct pci_dev *nb);
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int print_dmibar(struct pci_dev *nb);
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int print_pciexbar(struct pci_dev *nb);
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int print_pciexbar(struct pci_dev *nb);
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int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
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int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
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void ivybridge_dump_timings(void);
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@ -0,0 +1,382 @@
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/*
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 or (at your option) any later version of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <inttypes.h>
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#include "inteltool.h"
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extern volatile uint8_t *mchbar;
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static uint32_t read_mchbar32(uint32_t addr)
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{
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return *(volatile uint32_t *)(mchbar + addr);
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}
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static void
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print_time(const char *string, unsigned long long time, unsigned long long tCK)
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{
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printf(".%s = %lld /* %lld clocks = %.3lf ns */,\n",
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string, time, time, (time * tCK) / 256.0);
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}
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static unsigned int
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make_spd_time(unsigned long long time, unsigned long long tCK)
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{
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return (time * tCK) >> 5;
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}
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static u16 spd_ddr3_calc_crc(u8 * spd)
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{
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int n_crc, i;
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u8 *ptr;
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u16 crc;
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/* Find the number of bytes covered by CRC */
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if (spd[0] & 0x80) {
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n_crc = 117;
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} else {
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n_crc = 126;
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}
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/* Compute the CRC */
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crc = 0;
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ptr = spd;
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while (--n_crc >= 0) {
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crc = crc ^ (int)*ptr++ << 8;
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for (i = 0; i < 8; ++i)
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if (crc & 0x8000) {
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crc = crc << 1 ^ 0x1021;
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} else {
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crc = crc << 1;
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}
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}
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return crc;
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}
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void ivybridge_dump_timings(void)
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{
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u32 mr0[2];
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u32 mr1[2];
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u32 reg;
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unsigned int CAS = 0;
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int tWR = 0, tRFC = 0;
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int tFAW[2], tWTR[2], tCKE[2], tRTP[2], tRRD[2];
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int channel, slot;
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u32 reg_4004_b30[2] = { 0, 0 };
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unsigned int tREFI;
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int rankmap[2];
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u32 mad_dimm[2];
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unsigned int tRCD[2], tXP[2], tXPDLL[2], tRAS[2], tCWL[2], tRP[2],
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tAONPD[2];
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unsigned int tXSOffset;
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int two_channels = 1;
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struct slot_info {
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unsigned int size_mb;
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unsigned int ranks;
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unsigned int width;
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} slots[2][2];
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unsigned int tCK;
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u8 spd[2][2][256];
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memset(slots, 0, sizeof(slots));
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for (channel = 0; channel < 2; channel++) {
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rankmap[channel] = read_mchbar32(0xc14 + 0x100 * channel) >> 24;
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}
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two_channels = rankmap[0] && rankmap[1];
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mr0[0] = read_mchbar32(0x0004);
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mr1[0] = read_mchbar32(0x0008);
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mr0[1] = read_mchbar32(0x0104);
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mr1[1] = read_mchbar32(0x0108);
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if (mr0[0] != mr0[1] && two_channels)
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printf("MR0 mismatch: %x, %x\n", mr0[0], mr0[1]);
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if (mr1[0] != mr1[1] && two_channels)
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printf("MR1 mismatch: %x, %x\n", mr1[0], mr1[1]);
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reg = read_mchbar32(0x5e00) & ~0x80000000;
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printf(" .tCK = TCK_MHZ%d,\n", 400 * reg / 3);
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tCK = (64 * 10 * 3) / reg;
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if (mr0[0] & 1) {
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CAS = ((mr0[0] >> 4) & 0x7) + 12;
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} else {
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CAS = ((mr0[0] >> 4) & 0x7) + 4;
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}
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for (channel = 0; channel < 2; channel++) {
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mad_dimm[channel] = read_mchbar32(0x5004 + 4 * channel);
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}
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printf(".rankmap = { 0x%x, 0x%x }, \n", rankmap[0], rankmap[1]);
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printf(".mad_dimm = { 0x%x, 0x%x }, \n", mad_dimm[0], mad_dimm[1]);
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for (channel = 0; channel < 2; channel++)
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if (rankmap[channel]) {
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int ctWR;
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static const u8 mr0_wr_t[12] =
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{ 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 };
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reg = read_mchbar32(0x4004 + 0x400 * channel);
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ctWR = (reg >> 24) & 0x3f;
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if (tWR && ctWR != tWR)
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printf("/* tWR mismatch: %d, %d */\n", tWR,
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ctWR);
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if (!tWR)
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tWR = ctWR;
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if (((mr0[channel] >> 9) & 7) != mr0_wr_t[tWR - 5])
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printf("/* encoded tWR mismatch: %d, %d */\n",
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((mr0[channel] >> 9) & 7),
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mr0_wr_t[tWR - 5]);
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reg_4004_b30[channel] = reg >> 30;
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tFAW[channel] = (reg >> 16) & 0xff;
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tWTR[channel] = (reg >> 12) & 0xf;
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tCKE[channel] = (reg >> 8) & 0xf;
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tRTP[channel] = (reg >> 4) & 0xf;
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tRRD[channel] = (reg >> 0) & 0xf;
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reg = read_mchbar32(0x4000 + 0x400 * channel);
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tRAS[channel] = reg >> 16;
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tCWL[channel] = (reg >> 12) & 0xf;
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if (CAS != ((reg >> 8) & 0xf))
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printf("/* CAS mismatch: %d, %d. */\n", CAS,
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(reg >> 8) & 0xf);
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tRP[channel] = (reg >> 4) & 0xf;
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tRCD[channel] = reg & 0xf;
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reg = read_mchbar32(0x400c + channel * 0x400);
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tXPDLL[channel] = reg & 0x1f;
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tXP[channel] = (reg >> 5) & 7;
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tAONPD[channel] = (reg >> 8) & 0xff;
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}
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printf(".mobile = %d,\n", (mr0[0] >> 12) & 1);
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print_time("CAS", CAS, tCK);
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print_time("tWR", tWR, tCK);
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printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0],
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reg_4004_b30[1]);
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if (tFAW[0] != tFAW[1] && two_channels)
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printf("/* tFAW mismatch: %d, %d */\n", tFAW[0], tFAW[1]);
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print_time("tFAW", tFAW[0], tCK);
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if (tWTR[0] != tWTR[1] && two_channels)
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printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]);
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print_time("tWTR", tWTR[0], tCK);
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if (tCKE[0] != tCKE[1] && two_channels)
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printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]);
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print_time("tCKE", tCKE[0], tCK);
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if (tRTP[0] != tRTP[1] && two_channels)
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printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]);
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print_time("tRTP", tRTP[0], tCK);
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if (tRRD[0] != tRRD[1] && two_channels)
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printf("/* tRRD mismatch: %d, %d */\n", tRRD[0], tRRD[1]);
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print_time("tRRD", tRRD[0], tCK);
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if (tRAS[0] != tRAS[1] && two_channels)
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printf("/* tRAS mismatch: %d, %d */\n", tRAS[0], tRAS[1]);
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print_time("tRAS", tRAS[0], tCK);
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if (tCWL[0] != tCWL[1] && two_channels)
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printf("/* tCWL mismatch: %d, %d */\n", tCWL[0], tCWL[1]);
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print_time("tCWL", tCWL[0], tCK);
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if (tRP[0] != tRP[1] && two_channels)
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printf("/* tRP mismatch: %d, %d */\n", tRP[0], tRP[1]);
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print_time("tRP", tRP[0], tCK);
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if (tRCD[0] != tRCD[1] && two_channels)
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printf("/* tRCD mismatch: %d, %d */\n", tRCD[0], tRCD[1]);
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print_time("tRCD", tRCD[0], tCK);
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if (tXPDLL[0] != tXPDLL[1] && two_channels)
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printf("/* tXPDLL mismatch: %d, %d */\n", tXPDLL[0], tXPDLL[1]);
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print_time("tXPDLL", tXPDLL[0], tCK);
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if (tXP[0] != tXP[1] && two_channels)
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printf("/* tXP mismatch: %d, %d */\n", tXP[0], tXP[1]);
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print_time("tXP", tXP[0], tCK);
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if (tAONPD[0] != tAONPD[1] && two_channels)
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printf("/* tAONPD mismatch: %d, %d */\n", tAONPD[0], tAONPD[1]);
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print_time("tAONPD", tAONPD[0], tCK);
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reg = read_mchbar32(0x4298);
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if (reg != read_mchbar32(0x4698) && two_channels)
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printf("/* 4298 mismatch: %d, %d */\n", reg,
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read_mchbar32(0x4698));
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tREFI = reg & 0xffff;
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print_time("tREFI", tREFI, tCK);
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if ((tREFI * 9 / 1024) != (reg >> 25))
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printf("/* tREFI mismatch: %d, %d */\n", tREFI * 9 / 1024,
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(reg >> 25));
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tRFC = (reg >> 16) & 0x1ff;
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print_time("tRFC", tRFC, tCK);
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reg = read_mchbar32(0x42a4);
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if (reg != read_mchbar32(0x46a4) && two_channels)
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printf("/* 42a4 mismatch: %d, %d */\n", reg,
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read_mchbar32(0x46a4));
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print_time("tMOD", 8 + ((reg >> 28) & 0xf), tCK);
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tXSOffset = 512 - ((reg >> 16) & 0x3ff);
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print_time("tXSOffset", tXSOffset, tCK);
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if (tXSOffset != ((reg >> 12) & 0xf))
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printf("/* tXSOffset mismatch: %d, %d */\n",
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tXSOffset, (reg >> 12) & 0xf);
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if (512 != (reg & 0xfff))
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printf("/* tDLLK mismatch: %d, %d */\n", 512, reg & 0xfff);
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reg = read_mchbar32(0x5064);
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printf(".reg5064b0 = 0x%x,\n", reg & 0xfff);
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if ((reg >> 12) != 0x73)
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printf("/* mismatch 0x%x, 0x73. */\n", reg << 12);
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unsigned int ch0size, ch1size;
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switch (read_mchbar32(0x5000)) {
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case 0x24:
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reg = read_mchbar32(0x5014);
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ch1size = reg >> 24;
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if (((reg >> 16) & 0xff) != 2 * ch1size)
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printf("/* ch1size mismatch: %d, %d*/\n",
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2 * ch1size, ((ch1size >> 16) & 0xff));
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printf(".channel_size_mb = { ?, %d },\n", ch1size * 256);
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break;
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case 0x21:
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reg = read_mchbar32(0x5014);
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ch0size = reg >> 24;
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if (((reg >> 16) & 0xff) != 2 * ch0size)
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printf("/* ch0size mismatch: %d, %d*/\n",
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2 * ch0size, ((ch0size >> 16) & 0xff));
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printf(".channel_size_mb = { %d, ? },\n", ch0size * 256);
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break;
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}
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for (channel = 0; channel < 2; channel++) {
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reg = mad_dimm[channel];
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int swap = (reg >> 16) & 1;
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slots[channel][swap].size_mb = (reg & 0xff) * 256;
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slots[channel][swap].ranks = 1 + ((reg >> 17) & 1);
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slots[channel][swap].width = 8 + 8 * ((reg >> 19) & 1);
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slots[channel][!swap].size_mb = ((reg >> 8) & 0xff) * 256;
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slots[channel][!swap].ranks = 1 + ((reg >> 18) & 1);
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slots[channel][!swap].width = 8 + 8 * ((reg >> 20) & 1);
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}
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/* Undetermined: rank mirror, other modes, asr, ext_temp. */
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memset(spd, 0, sizeof(spd));
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for (channel = 0; channel < 2; channel++)
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for (slot = 0; slot < 2; slot++)
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if (slots[channel][slot].size_mb) {
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printf("/* CH%dS%d: %d MiB */\n", channel,
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slot, slots[channel][slot].size_mb);
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}
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for (channel = 0; channel < 2; channel++)
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for (slot = 0; slot < 2; slot++)
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if (slots[channel][slot].size_mb) {
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int capacity_shift;
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unsigned int ras, rc, rfc, faw;
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u16 crc;
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capacity_shift =
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ffs(slots[channel][slot].size_mb *
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slots[channel][slot].width /
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(slots[channel][slot].ranks * 64)) - 1 -
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5;
|
||||||
|
|
||||||
|
spd[channel][slot][0] = 0x92;
|
||||||
|
spd[channel][slot][1] = 0x11;
|
||||||
|
spd[channel][slot][2] = 0xb; /* DDR3 */
|
||||||
|
spd[channel][slot][3] = 3; /* SODIMM, should we use another type for desktop? */
|
||||||
|
spd[channel][slot][4] = capacity_shift | 0; /* 8 Banks. */
|
||||||
|
spd[channel][slot][5] = 0; /* FIXME */
|
||||||
|
spd[channel][slot][6] = 0; /* FIXME */
|
||||||
|
spd[channel][slot][7] =
|
||||||
|
((slots[channel][slot].ranks -
|
||||||
|
1) << 3) | (ffs(slots[channel][slot].
|
||||||
|
width) - 1 - 2);
|
||||||
|
spd[channel][slot][8] = 3; /* Bus width 64b. No ECC yet. */
|
||||||
|
spd[channel][slot][9] = 0x52; /* 2.5ps. FIXME: choose dynamically if needed. */
|
||||||
|
spd[channel][slot][10] = 0x01;
|
||||||
|
spd[channel][slot][11] = 0x08; /* 1/8 ns. FIXME: choose dynamically if needed. */
|
||||||
|
spd[channel][slot][12] = make_spd_time(1, tCK);
|
||||||
|
spd[channel][slot][13] = 0;
|
||||||
|
spd[channel][slot][14] =
|
||||||
|
(1 << (CAS - 4)) & 0xff;
|
||||||
|
spd[channel][slot][15] = (1 << (CAS - 4)) >> 8;
|
||||||
|
spd[channel][slot][16] =
|
||||||
|
make_spd_time(CAS, tCK);
|
||||||
|
spd[channel][slot][17] =
|
||||||
|
make_spd_time(tWR, tCK);
|
||||||
|
spd[channel][slot][18] =
|
||||||
|
make_spd_time(tRCD[channel], tCK);
|
||||||
|
spd[channel][slot][19] =
|
||||||
|
make_spd_time(tRRD[channel], tCK);
|
||||||
|
spd[channel][slot][20] =
|
||||||
|
make_spd_time(tRP[channel], tCK);
|
||||||
|
ras = make_spd_time(tRAS[channel], tCK);
|
||||||
|
rc = 0x181; /* FIXME: should be make_spd_time(tRC, tCK). */
|
||||||
|
spd[channel][slot][22] = ras;
|
||||||
|
spd[channel][slot][23] = rc;
|
||||||
|
spd[channel][slot][21] =
|
||||||
|
((ras >> 8) & 0xf) | ((rc >> 4) & 0xf0);
|
||||||
|
rfc = make_spd_time(tRFC, tCK);
|
||||||
|
spd[channel][slot][24] = rfc;
|
||||||
|
spd[channel][slot][25] = rfc >> 8;
|
||||||
|
spd[channel][slot][26] =
|
||||||
|
make_spd_time(tWTR[channel], tCK);
|
||||||
|
spd[channel][slot][27] =
|
||||||
|
make_spd_time(tRTP[channel], tCK);
|
||||||
|
faw = make_spd_time(tFAW[channel], tCK);
|
||||||
|
spd[channel][slot][28] = faw >> 8;
|
||||||
|
spd[channel][slot][29] = faw;
|
||||||
|
spd[channel][slot][30] = 0; /* FIXME */
|
||||||
|
spd[channel][slot][31] = 0; /* FIXME */
|
||||||
|
spd[channel][slot][32] = 0; /* FIXME */
|
||||||
|
spd[channel][slot][33] = 0; /* FIXME */
|
||||||
|
spd[channel][slot][62] = 0x65; /* Reference card F. FIXME */
|
||||||
|
spd[channel][slot][63] = 0; /* FIXME */
|
||||||
|
crc = spd_ddr3_calc_crc(spd[channel][slot]);
|
||||||
|
spd[channel][slot][126] = crc;
|
||||||
|
spd[channel][slot][127] = crc >> 8;
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("/* SPD matching current mode: */\n");
|
||||||
|
|
||||||
|
for (channel = 0; channel < 2; channel++)
|
||||||
|
for (slot = 0; slot < 2; slot++)
|
||||||
|
if (slots[channel][slot].size_mb) {
|
||||||
|
int i;
|
||||||
|
|
||||||
|
printf("/* CH%dS%d */\n", channel, slot);
|
||||||
|
|
||||||
|
for (i = 0; i < 256; i++) {
|
||||||
|
if ((i & 0xf) == 0x0)
|
||||||
|
printf("%02x: ", i);
|
||||||
|
printf("%02x ", spd[channel][slot][i]);
|
||||||
|
if ((i & 0xf) == 0xf)
|
||||||
|
printf("\n");
|
||||||
|
}
|
||||||
|
printf("\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -214,6 +214,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
|
||||||
mchbar_phys = pci_read_long(nb, 0x48);
|
mchbar_phys = pci_read_long(nb, 0x48);
|
||||||
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
|
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
|
||||||
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
|
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
|
||||||
|
size = 32768;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
|
printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
|
||||||
|
|
@ -240,9 +241,19 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
|
||||||
printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i));
|
printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (nb->device_id == PCI_DEVICE_ID_INTEL_CORE_1ST_GEN) {
|
switch (nb->device_id)
|
||||||
|
{
|
||||||
|
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
|
||||||
printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
|
printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
|
||||||
dump_timings ();
|
dump_timings ();
|
||||||
|
break;
|
||||||
|
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A:
|
||||||
|
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
|
||||||
|
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
|
||||||
|
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
|
||||||
|
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
|
||||||
|
ivybridge_dump_timings();
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
unmap_physical((void *)mchbar, size);
|
unmap_physical((void *)mchbar, size);
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue