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treewide: capitalize 'USB' 

Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-02-24 13:26:04 +01:00 committed by Patrick Georgi
parent dfd3f21174
commit 44f558ec26
26 changed files with 47 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
payloads/libpayload/drivers/udc/chipidea.c
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@ -81,7 +81,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg,
memcpy(&this->device_descriptor, dd, sizeof(*dd)); memcpy(&this->device_descriptor, dd, sizeof(*dd));
if (p->qhlist == NULL) if (p->qhlist == NULL)
die("failed to allocate memory for usb device mode"); die("failed to allocate memory for USB device mode");
memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS); memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS);
@ -102,7 +102,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg,
p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS;
do { do {
debug("waiting for usb phy clk valid: %x\n", debug("waiting for USB phy clk valid: %x\n",
readl(&p->opreg->susp_ctrl)); readl(&p->opreg->susp_ctrl));
mdelay(1); mdelay(1);
} while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0); } while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0);

2
payloads/libpayload/drivers/udc/chipidea_priv.h
View File

@ -47,7 +47,7 @@ struct chipidea_opreg {
uint32_t portsc; // 0x174 uint32_t portsc; // 0x174
uint32_t pad178[15]; uint32_t pad178[15];
uint32_t devlc; // 0x1b4 uint32_t devlc; // 0x1b4
/* 25:26: host-desired usb version /* 25:26: host-desired USB version
* 23: force full speed */ * 23: force full speed */
uint32_t pad1b8[16]; uint32_t pad1b8[16];
uint32_t usbmode; // 0x1f8 uint32_t usbmode; // 0x1f8

2
payloads/libpayload/drivers/usb/ehci.c
View File

@ -291,7 +291,7 @@ static int ehci_set_async_schedule(ehci_t *ehcic, int enable)
/* Memory barrier to ensure that all memory accesses before we set the /* Memory barrier to ensure that all memory accesses before we set the
* async schedule are complete. It was observed especially in the case of * async schedule are complete. It was observed especially in the case of
* arm64, that netboot and usb stuff resulted in lots of errors possibly * arm64, that netboot and USB stuff resulted in lots of errors possibly
* due to CPU reordering. Hence, enforcing strict CPU ordering. * due to CPU reordering. Hence, enforcing strict CPU ordering.
*/ */
mb(); mb();

4
payloads/libpayload/drivers/usb/usb.c
View File

@ -634,14 +634,14 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr)
/* /*
* Should be called by the hub drivers whenever a physical detach occurs * Should be called by the hub drivers whenever a physical detach occurs
* and can be called by usb class drivers if they are unsatisfied with a * and can be called by USB class drivers if they are unsatisfied with a
* malfunctioning device. * malfunctioning device.
*/ */
void void
usb_detach_device(hci_t *controller, int devno) usb_detach_device(hci_t *controller, int devno)
{ {
/* check if device exists, as we may have /* check if device exists, as we may have
been called yet by the usb class driver */ been called yet by the USB class driver */
if (controller->devices[devno]) { if (controller->devices[devno]) {
controller->devices[devno]->destroy (controller->devices[devno]); controller->devices[devno]->destroy (controller->devices[devno]);

8
payloads/libpayload/drivers/usb/usbmsc.c
View File

@ -126,7 +126,7 @@ enum {
* MSC commands can be * MSC commands can be
* successful, * successful,
* fail with proper response or * fail with proper response or
* fail totally, which results in detaching of the usb device * fail totally, which results in detaching of the USB device
* and immediate cleanup of the usbdev_t structure. * and immediate cleanup of the usbdev_t structure.
* In the latter case the caller has to make sure, that he won't * In the latter case the caller has to make sure, that he won't
* use the device any more. * use the device any more.
@ -703,14 +703,14 @@ usb_msc_poll (usbdev_t *dev)
return; return;
if (!prev_ready && msc->ready) { if (!prev_ready && msc->ready) {
usb_debug ("usb msc: not ready -> ready (lun %d)\n", msc->lun); usb_debug ("USB msc: not ready -> ready (lun %d)\n", msc->lun);
usb_msc_create_disk (dev); usb_msc_create_disk (dev);
} else if (prev_ready && !msc->ready) { } else if (prev_ready && !msc->ready) {
usb_debug ("usb msc: ready -> not ready (lun %d)\n", msc->lun); usb_debug ("USB msc: ready -> not ready (lun %d)\n", msc->lun);
usb_msc_remove_disk (dev); usb_msc_remove_disk (dev);
} else if (!prev_ready && !msc->ready) { } else if (!prev_ready && !msc->ready) {
u8 new_lun = (msc->lun + 1) % msc->num_luns; u8 new_lun = (msc->lun + 1) % msc->num_luns;
usb_debug("usb msc: not ready (lun %d) -> lun %d\n", msc->lun, usb_debug("USB msc: not ready (lun %d) -> lun %d\n", msc->lun,
new_lun); new_lun);
msc->lun = new_lun; msc->lun = new_lun;
} }

4
payloads/libpayload/include/usb/usb.h
View File

@ -217,7 +217,7 @@ struct usbdev {
hci_t *controller; hci_t *controller;
endpoint_t endpoints[32]; endpoint_t endpoints[32];
int num_endp; int num_endp;
int address; // usb address int address; // USB address
int hub; // hub, device is attached to int hub; // hub, device is attached to
int port; // port where device is attached int port; // port where device is attached
usb_speed speed; usb_speed speed;
@ -263,7 +263,7 @@ struct usbdev_hc {
u8* (*poll_intr_queue) (void *queue); u8* (*poll_intr_queue) (void *queue);
void *instance; void *instance;
/* set_address(): Tell the usb device its address (xHCI /* set_address(): Tell the USB device its address (xHCI
controllers want to do this by controllers want to do this by
themselves). Also, allocate the usbdev themselves). Also, allocate the usbdev
structure, initialize enpoint 0 structure, initialize enpoint 0

2
src/drivers/usb/ehci_debug.c
View File

@ -382,7 +382,7 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
u32 portsc; u32 portsc;
int loop; int loop;
/* Reset the usb debug port */ /* Reset the USB debug port */
portsc = read32(&ehci_regs->port_status[port - 1]); portsc = read32(&ehci_regs->port_status[port - 1]);
portsc &= ~PORT_PE; portsc &= ~PORT_PE;
portsc |= PORT_RESET; portsc |= PORT_RESET;

4
src/mainboard/google/butterfly/early_init.c
View File

@ -67,7 +67,7 @@ void mainboard_late_rcba_config(void)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */ /* enabled power USB oc pin */
{ 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */
{ 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */
{ 1, 0, -1 }, /* P2: Camera (no OC) */ { 1, 0, -1 }, /* P2: Camera (no OC) */
@ -120,7 +120,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dimm_channel1_disabled = 2, .dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600, .max_ddr3_freq = 1600,
.usb_port_config = { .usb_port_config = {
/* enabled usb oc pin length */ /* enabled USB oc pin length */
{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
{ 1, 0, 0x0040 }, /* P2: Camera (no OC) */ { 1, 0, 0x0040 }, /* P2: Camera (no OC) */

2
src/mainboard/google/link/early_init.c
View File

@ -154,7 +154,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */ /* enabled power USB oc pin */
{ 0, 0, -1 }, /* P0: Empty */ { 0, 0, -1 }, /* P0: Empty */
{ 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
{ 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */

2
src/mainboard/google/mistral/mainboard.c
View File

@ -26,7 +26,7 @@ static struct usb_board_data usb1_board_data = {
static void setup_usb(void) static void setup_usb(void)
{ {
/* Setting Secondary usb controller */ /* Setting Secondary USB controller */
setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data);
} }

2
src/mainboard/google/oak/mainboard.c
View File

@ -145,7 +145,7 @@ static void configure_usb(void)
static void configure_usb_hub(void) static void configure_usb_hub(void)
{ {
/* set usb hub reset pin (low active) to high */ /* set USB hub reset pin (low active) to high */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
gpio_output(GPIO(UTXD3), 1); gpio_output(GPIO(UTXD3), 1);
} }

2
src/mainboard/google/parrot/early_init.c
View File

@ -116,7 +116,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */ /* enabled power USB oc pin */
{ 0, 0, -1 }, /* P0: Empty */ { 0, 0, -1 }, /* P0: Empty */
{ 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
{ 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */

4
src/mainboard/google/stout/early_init.c
View File

@ -131,7 +131,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dimm_channel1_disabled = 2, .dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600, .max_ddr3_freq = 1600,
.usb_port_config = { .usb_port_config = {
/* enabled usb oc pin length */ /* enabled USB oc pin length */
{ 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */
{ 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */
{ 0, 1, 0x0000 }, /* P2: Empty */ { 0, 1, 0x0000 }, /* P2: Empty */
@ -171,7 +171,7 @@ int mainboard_should_reset_usb(int s3resume)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled usb oc pin length */ /* enabled USB oc pin length */
{1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */
{1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */
{0, 0, 0}, /* P2: Empty */ {0, 0, 0}, /* P2: Empty */

2
src/mainboard/intel/emeraldlake2/early_init.c
View File

@ -111,7 +111,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */ /* enabled power USB oc pin */
{ 1, 0, 0 }, /* P0: Front port (OC0) */ { 1, 0, 0 }, /* P0: Front port (OC0) */
{ 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, 1 }, /* P1: Back port (OC1) */
{ 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */

10
src/mainboard/intel/harcuvar/hsio.h
View File

@ -38,7 +38,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
* Lane[19]->USB3 rear I/O panel connector * Lane[19]->USB3 rear I/O panel connector
*/ */
/* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */ /* SKU HSIO 20 (pcie [0-15] sata [16-18] USB [19]) */
{BL_SKU_HSIO_20, {BL_SKU_HSIO_20,
{PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4}, {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */
@ -155,7 +155,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */ /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] USB [19]) */
{BL_SKU_HSIO_12, {BL_SKU_HSIO_12,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/*ME_FIA_MUX_CONFIG */ {/*ME_FIA_MUX_CONFIG */
@ -272,7 +272,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */ /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] USB [19]) */
{BL_SKU_HSIO_10, {BL_SKU_HSIO_10,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */
@ -388,7 +388,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */ /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] USB [19]) */
{BL_SKU_HSIO_08, {BL_SKU_HSIO_08,
{PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */
@ -504,7 +504,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */ /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] USB [19]) */
{BL_SKU_HSIO_06, {BL_SKU_HSIO_06,
{PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */

4
src/mainboard/kontron/ktqm77/early_init.c
View File

@ -99,7 +99,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dimm_channel1_disabled = 2, .dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600, .max_ddr3_freq = 1600,
.usb_port_config = { .usb_port_config = {
/* enabled usb oc pin length */ /* enabled USB oc pin length */
{ 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */
{ 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */
{ 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */
@ -127,7 +127,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */ /* enabled power USB oc pin */
{ 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */
{ 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */
{ 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */

8
src/mainboard/lenovo/t430s/variants/t431s/romstage.c
View File

@ -26,9 +26,9 @@
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 }, /* SSP1: right */ { 1, 0, 0 }, /* SSP1: right */
{ 1, 0, 1 }, /* SSP2: left, EHCI Debug */ { 1, 0, 1 }, /* SSP2: left, EHCI Debug */
{ 1, 1, 3 }, /* SSP3: dock usb3 */ { 1, 1, 3 }, /* SSP3: dock USB3 */
{ 1, 1, -1 }, /* B0P4: wwan usb */ { 1, 1, -1 }, /* B0P4: wwan USB */
{ 1, 1, 2 }, /* B0P5: dock usb2 */ { 1, 1, 2 }, /* B0P5: dock USB2 */
{ 0, 0, -1 }, /* B0P6 */ { 0, 0, -1 }, /* B0P6 */
{ 0, 0, -1 }, /* B0P7 */ { 0, 0, -1 }, /* B0P7 */
{ 1, 2, -1 }, /* B0P8: unknown */ { 1, 2, -1 }, /* B0P8: unknown */
@ -36,7 +36,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 0, 2, 5 }, /* B1P2 */ { 0, 2, 5 }, /* B1P2 */
{ 1, 1, -1 }, /* B1P3: fingerprint reader */ { 1, 1, -1 }, /* B1P3: fingerprint reader */
{ 0, 0, -1 }, /* B1P4 */ { 0, 0, -1 }, /* B1P4 */
{ 1, 1, -1 }, /* B1P5: wlan usb */ { 1, 1, -1 }, /* B1P5: wlan USB */
{ 1, 1, -1 }, /* B1P6: Camera */ { 1, 1, -1 }, /* B1P6: Camera */
}; };

2
src/mainboard/samsung/lumpy/early_init.c
View File

@ -178,7 +178,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */ /* enabled power USB oc pin */
{ 1, 1, 0 }, /* P0: Port 0 (OC0) */ { 1, 1, 0 }, /* P0: Port 0 (OC0) */
{ 1, 1, 1 }, /* P1: Port 1 (OC1) */ { 1, 1, 1 }, /* P1: Port 1 (OC1) */
{ 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */

2
src/mainboard/samsung/stumpy/early_init.c
View File

@ -167,7 +167,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
} }
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */ /* enabled power USB oc pin */
{ 1, 1, 0 }, /* P0: Front port (OC0) */ { 1, 1, 0 }, /* P0: Front port (OC0) */
{ 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, 1 }, /* P1: Back port (OC1) */
{ 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */

10
src/mainboard/scaleway/tagada/hsio.h
View File

@ -38,7 +38,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = {
* Lane[19]->USB3 rear I/O panel connector * Lane[19]->USB3 rear I/O panel connector
*/ */
/* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */ /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] USB [19]) */
{BL_SKU_HSIO_20, {BL_SKU_HSIO_20,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */
@ -155,7 +155,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */ /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] USB [19]) */
{BL_SKU_HSIO_12, {BL_SKU_HSIO_12,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */
@ -273,7 +273,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */ /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] USB [19]) */
{BL_SKU_HSIO_10, {BL_SKU_HSIO_10,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */
@ -391,7 +391,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */ /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] USB [19]) */
{BL_SKU_HSIO_08, {BL_SKU_HSIO_08,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */
@ -509,7 +509,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = {
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
BL_FIA_PCIE_ROOT_PORT_7)} } }, BL_FIA_PCIE_ROOT_PORT_7)} } },
/* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */ /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] USB []) */
{BL_SKU_HSIO_06, {BL_SKU_HSIO_06,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */ {/* ME_FIA_MUX_CONFIG */

2
src/soc/intel/apollolake/chip.c
View File

@ -842,7 +842,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
/* /*
* Override GLK xhci clock gating register(XHCLKGTEN) to * Override GLK xhci clock gating register(XHCLKGTEN) to
* mitigate usb device suspend and resume failure. * mitigate USB device suspend and resume failure.
*/ */
if (CONFIG(SOC_INTEL_GLK)) { if (CONFIG(SOC_INTEL_GLK)) {
uint32_t *cfg; uint32_t *cfg;

4
src/soc/intel/common/block/xhci/elog.c
View File

@ -84,7 +84,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event)
/* /*
* Check if CSC bit is set and port is capable of wake on * Check if CSC bit is set and port is capable of wake on
* connect/disconnect to identify if the port caused wake * connect/disconnect to identify if the port caused wake
* event for usb attach/detach. * event for USB attach/detach.
*/ */
if (pch_xhci_csc_set(port_status) && if (pch_xhci_csc_set(port_status) &&
pch_xhci_wake_capable(port_status)) { pch_xhci_wake_capable(port_status)) {
@ -95,7 +95,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event)
/* /*
* Check if PLC is set and PLS indicates resume to identify if * Check if PLC is set and PLS indicates resume to identify if
* the port caused wake event for usb activity. * the port caused wake event for USB activity.
*/ */
if (pch_xhci_plc_set(port_status) && if (pch_xhci_plc_set(port_status) &&
pch_xhci_resume(port_status)) { pch_xhci_resume(port_status)) {

2
src/soc/mediatek/common/usb.c
View File

@ -104,7 +104,7 @@ static int check_ip_clk_status(void)
do { do {
if (stopwatch_expired(&sw)) { if (stopwatch_expired(&sw)) {
u3p_err("usb clocks are not stable!!!\n"); u3p_err("USB clocks are not stable!!!\n");
return -1; return -1;
} }

2
src/southbridge/amd/cimx/sb800/late.c
View File

@ -214,7 +214,7 @@ static struct device_operations usb_ops = {
}; };
/* /*
* The pci id of usb ctrl 0 and 1 are the same. * The pci id of USB ctrl 0 and 1 are the same.
*/ */
static const struct pci_driver usb_ohci123_driver __pci_driver = { static const struct pci_driver usb_ohci123_driver __pci_driver = {
.ops = &usb_ops, .ops = &usb_ops,

2
src/southbridge/intel/i82801gx/early_init.c
View File

@ -99,7 +99,7 @@ void i82801gx_early_init(void)
reg8 &= ~RTC_BATTERY_DEAD; reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* usb transient disconnect */ /* USB transient disconnect */
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
reg8 |= (3 << 0); reg8 |= (3 << 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);

2
util/uio_usbdebug/uio_usbdebug_intel.c
View File

@ -52,7 +52,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{ {
/* claim usb debug port */ /* claim USB debug port */
const unsigned long dbgctl_addr = const unsigned long dbgctl_addr =
((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET; ((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET;
write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30)); write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30));