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soc/intel/apollolake: Configure a GPIO for TPM in bootblock 

One of devices connected to FAST SPI bus is TPM. SoC uses dedicated
line for chip select for TPM function. If TPM is used, that line needs
to be configured to a specific native funciton.

Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14467
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-04-18 13:36:19 -07:00 committed by Aaron Durbin
parent 1ba068550d
commit 4520c5e757
3 changed files with 15 additions and 35 deletions
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3
src/mainboard/intel/apollolake_rvp/Makefile.inc
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@ -1,3 +1,2 @@
bootblock-$(CONFIG_LPC_TPM) += bootblock.c #Nothing here yet

33
src/mainboard/intel/apollolake_rvp/bootblock.c
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@ -1,33 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <soc/gpio.h>
static const struct pad_config tpm_spi_configs[] = {
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
};
static void tpm_enable(void)
{
/* Configure gpios */
gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
}
void bootblock_mainboard_init(void) {
if (IS_ENABLED(CONFIG_LPC_TPM))
tpm_enable();
}

14
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@ -19,10 +19,21 @@
#include <device/pci.h> #include <device/pci.h>
#include <soc/bootblock.h> #include <soc/bootblock.h>
#include <soc/cpu.h> #include <soc/cpu.h>
#include <soc/gpio.h>
#include <soc/northbridge.h> #include <soc/northbridge.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/uart.h> #include <soc/uart.h>
static const struct pad_config tpm_spi_configs[] = {
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
};
static void tpm_enable(void)
{
/* Configure gpios */
gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
}
void asmlinkage bootblock_c_entry(void) void asmlinkage bootblock_c_entry(void)
{ {
device_t dev = NB_DEV_ROOT; device_t dev = NB_DEV_ROOT;
@ -45,4 +56,7 @@ void bootblock_soc_early_init(void)
/* Prepare UART for serial console. */ /* Prepare UART for serial console. */
if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
soc_console_uart_init(); soc_console_uart_init();
if (IS_ENABLED(CONFIG_LPC_TPM))
tpm_enable();
} }