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soc/amd/picasso/tsc: fix clock divisor range check 

The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.

TEST=Compared with Picasso's PPR #55570

Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2020-12-04 01:59:15 +01:00 committed by Patrick Georgi
parent c6ef514e93
commit 455d7b74ab
1 changed files with 1 additions and 1 deletions
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2
src/soc/amd/picasso/tsc_freq.c
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@ -33,7 +33,7 @@ unsigned long tsc_freq_mhz(void)
if (!cpudid) { if (!cpudid) {
mhz = TSC_DEFAULT_FREQ_MHZ; mhz = TSC_DEFAULT_FREQ_MHZ;
printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz); printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz);
} else if ((cpudid >= 8) && (cpudid < 0x3c)) { } else if ((cpudid >= 8) && (cpudid <= 0x30)) {
mhz = (200 * cpufid) / cpudid; mhz = (200 * cpufid) / cpudid;
} else { } else {
mhz = 25 * cpufid; mhz = 25 * cpufid;