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soc/intel/{APL,GLK}: Use Intel SRAM common code 

TEST:Build and boot reef. Verified that SRAM common code
is used to set the resources.

Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/22608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
V Sowmya 2017-11-27 12:39:10 +05:30 committed by Subrata Banik
parent c333b98fb8
commit 45a21381d6
3 changed files with 1 additions and 74 deletions
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1
src/soc/intel/apollolake/Kconfig
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@ -78,6 +78,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_P2SB
select SOC_INTEL_COMMON_BLOCK_PMC
select SOC_INTEL_COMMON_BLOCK_SRAM
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS

1
src/soc/intel/apollolake/Makefile.inc
View File

@ -62,7 +62,6 @@ ramstage-y += systemagent.c
ramstage-y += pmutil.c
ramstage-y += pmc.c
ramstage-y += reset.c
ramstage-y += sram.c
ramstage-y += xdci.c
ramstage-y += sd.c

73
src/soc/intel/apollolake/sram.c
View File

@ -1,73 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/pci_devs.h>
#include <soc/iomap.h>
static void read_resources(device_t dev)
{
struct resource *res;
pci_dev_read_resources(dev);
res = new_resource(dev, PCI_BASE_ADDRESS_0);
res->base = SRAM_BASE_0;
res->size = SRAM_SIZE_0;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, PCI_BASE_ADDRESS_2);
res->base = SRAM_BASE_2;
res->size = SRAM_SIZE_2;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void set_resources(device_t dev)
{
struct resource *res;
pci_dev_set_resources(dev);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
pci_write_config32(dev, res->index, res->base);
dev->command |= PCI_COMMAND_MEMORY;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, " SRAM BAR 0");
res = find_resource(dev, PCI_BASE_ADDRESS_2);
pci_write_config32(dev, res->index, res->base);
dev->command |= PCI_COMMAND_MEMORY;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, " SRAM BAR 2");
}
static const struct device_operations device_ops = {
.read_resources = read_resources,
.set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
};
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_APL_SRAM,
PCI_DEVICE_ID_INTEL_GLK_SRAM,
0,
};
static const struct pci_driver pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices= pci_device_ids,
};