mb/google/zork: Update ramstage GPIOs for v3 schematics for dalboz reference
This change updates the baseboard GPIO table in ramstage to match v3 version of dalboz reference schematics. All variants using this reference are accordingly updated to configure the GPIOs that changed as part of v3 schematics. BUG=b:157165628, b:157744136, b:157743835 TEST=Compiles Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: If9d0e35801f9f9b15eddeb4ec7068fed6d401307 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251394 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Auto-Submit: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -103,8 +103,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
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PAD_GPI(GPIO_4, PULL_UP),
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/* PEN_POWER_EN - Enabled*/
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PAD_GPO(GPIO_5, HIGH),
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/* DMIC_SEL */
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PAD_GPO(GPIO_6, LOW), // Select Camera 1 Dmic
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/* EN_PWR_TOUCHPAD */
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PAD_GPO(GPIO_6, HIGH),
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/* I2S_SDIN */
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PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
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/* I2S_LRCLK - Bit banged in depthcharge */
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@ -134,12 +134,12 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
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PAD_GPI(GPIO_31, PULL_UP),
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/* */
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PAD_GPI(GPIO_32, PULL_DOWN),
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/* EN_PWR_TOUCHPAD_PS2 */
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/* DMIC_SEL */
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/*
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* EN_PWR_TOUCHPAD_PS2 - Make sure Ext ROM Sharing is disabled before
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* using this GPIO. Otherwise SPI flash access will be very slow.
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* Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash
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* access will be very slow.
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*/
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PAD_GPO(GPIO_67, HIGH),
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PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic
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/* EMMC_RESET */
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PAD_GPO(GPIO_68, LOW),
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/* RAM ID 3*/
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@ -9,12 +9,23 @@
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/* This table is used by dalboz variant with board version < 2. */
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static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
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/* DMIC_SEL */
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PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
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/* USB_OC2_L - USB A0 & A1 */
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PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
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/* EN_PWR_TOUCHPAD_PS2 */
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PAD_GPO(GPIO_67, HIGH),
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/* Unused */
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PAD_GPI(GPIO_143, PULL_DOWN),
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};
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static const struct soc_amd_gpio bid_2_gpio_set_stage_ram[] = {
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/* DMIC_SEL */
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PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
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/* EN_PWR_TOUCHPAD_PS2 */
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PAD_GPO(GPIO_67, HIGH),
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};
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const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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{
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uint32_t board_version;
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@ -30,6 +41,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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if (board_version < 2) {
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*size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
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return bid_1_gpio_set_stage_ram;
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} else if (board_version == 2) {
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*size = ARRAY_SIZE(bid_2_gpio_set_stage_ram);
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return bid_2_gpio_set_stage_ram;
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}
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*size = 0;
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@ -3,3 +3,4 @@
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subdirs-y += ./spd
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ramstage-y += variant.c
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ramstage-y += gpio.c
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@ -0,0 +1,37 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <ec/google/chromeec/ec.h>
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/* This table is used by dalboz variant with board version < 2. */
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static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
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/* DMIC_SEL */
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PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
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/* EN_PWR_TOUCHPAD_PS2 */
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PAD_GPO(GPIO_67, HIGH),
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};
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const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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{
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uint32_t board_version;
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/*
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* If board version cannot be read, assume that this is an older revision of the board
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* and so apply overrides. If board version is provided by the EC, then apply overrides
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* if version < 2.
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*/
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if (google_chromeec_cbi_get_board_version(&board_version))
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board_version = 1;
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if (board_version < 2) {
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*size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
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return bid_1_gpio_set_stage_ram;
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}
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*size = 0;
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return NULL;
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}
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