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mb/google/zork: Update ramstage GPIOs for v3 schematics for trembyle reference 

This change updates the baseboard GPIO table in ramstage to match v3
version of trembyle reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.

BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-06-18 01:34:48 -07:00
parent c699255ba5
commit da459c46bd
5 changed files with 105 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@ -115,8 +115,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_GPO(GPIO_11, HIGH),
/* USI_INT_ODL */
PAD_GPI(GPIO_12, PULL_UP),
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_13, HIGH),
/* BT_DISABLE */
PAD_GPO(GPIO_14, LOW),
/* USB_OC0_L - USB C0 + USB A0 */
@ -135,12 +135,12 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_GPI(GPIO_31, PULL_UP),
/* EN_PWR_FP */
PAD_GPO(GPIO_32, HIGH),
/* EN_PWR_TOUCHPAD_PS2 */
/* DMIC SEL */
/*
* EN_PWR_TOUCHPAD_PS2 - Make sure Ext ROM Sharing is disabled before
* using this GPIO. Otherwise SPI flash access will be very slow.
* Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash
* access will be very slow.
*/
PAD_GPO(GPIO_67, HIGH),
PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic
/* EMMC_RESET */
PAD_GPO(GPIO_68, LOW),
/* FPMCU_BOOT0 - TODO: Check this */
@ -155,16 +155,14 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_GPO(GPIO_76, HIGH),
/* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */
PAD_GPO(GPIO_85, HIGH),
/* MST_GPIO_2 (Fw Update HDMI hub) */
PAD_GPI(GPIO_86, PULL_NONE),
/* EMMC_DATA7 */
PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE),
/* EMMC_DATA5 */
PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE),
/* EN_DEV_BEEP_L */
PAD_GPO(GPIO_89, HIGH),
/* MST_GPIO_3 (Fw Update HDMI hub) */
PAD_GPI(GPIO_90, PULL_NONE),
/* Testpoint */
PAD_GPI(GPIO_90, PULL_UP),
/* EN_SPKR TODO: Verify driver enables this (add to ACPI) */
PAD_GPO(GPIO_91, LOW),
/* EMMC_DATA0 */

16
src/mainboard/google/zork/variants/berknip/gpio.c
View File

@ -6,12 +6,22 @@
#include <gpio.h>
#include <soc/gpio.h>
#include <ec/google/chromeec/ec.h>
static const struct soc_amd_gpio berknip_v1_gpio_set_stage_ram[] = {
static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = {
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* USB_OC4_L - USB_A1 */
PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
/* USB_OC2_L - USB A0 */
PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_67, HIGH),
/* MST_GPIO_2 (Fw Update HDMI hub) */
PAD_GPI(GPIO_86, PULL_NONE),
/* MST_GPIO_3 (Fw Update HDMI hub) */
PAD_GPI(GPIO_90, PULL_NONE),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{
uint32_t board_version;
@ -25,8 +35,8 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
board_version = 1;
if (board_version <= 1) {
*size = ARRAY_SIZE(berknip_v1_gpio_set_stage_ram);
return berknip_v1_gpio_set_stage_ram;
*size = ARRAY_SIZE(berknip_bid1_gpio_set_stage_ram);
return berknip_bid1_gpio_set_stage_ram;
}
*size = 0;

45
src/mainboard/google/zork/variants/ezkinil/gpio.c
View File

@ -6,12 +6,44 @@
#include <gpio.h>
#include <soc/gpio.h>
#include <ec/google/chromeec/ec.h>
static const struct soc_amd_gpio ezkinil_v1_gpio_set_stage_ram[] = {
static const struct soc_amd_gpio ezkinil_bid1_gpio_set_stage_ram[] = {
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* USB_OC4_L - USB_A1 */
PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
/* USB_OC2_L - USB A0 */
PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_67, HIGH),
/* MST_GPIO_2 (Fw Update HDMI hub) */
PAD_GPI(GPIO_86, PULL_NONE),
/* MST_GPIO_3 (Fw Update HDMI hub) */
PAD_GPI(GPIO_90, PULL_NONE),
};
static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = {
/* FPMCU_RST_L Change NC */
PAD_GPI(GPIO_11, PULL_UP),
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_67, HIGH),
/* FPMCU_BOOT0 Change NC */
PAD_GPI(GPIO_69, PULL_UP),
/* MST_GPIO_2 (Fw Update HDMI hub) Change NC */
PAD_GPI(GPIO_86, PULL_UP),
};
static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = {
/* FPMCU_RST_L Change NC */
PAD_GPI(GPIO_11, PULL_UP),
/* FPMCU_BOOT0 Change NC */
PAD_GPI(GPIO_69, PULL_UP),
/* MST_GPIO_2 (Fw Update HDMI hub) Change NC */
PAD_GPI(GPIO_86, PULL_UP),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{
uint32_t board_version;
@ -25,10 +57,13 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
board_version = 1;
if (board_version <= 1) {
*size = ARRAY_SIZE(ezkinil_v1_gpio_set_stage_ram);
return ezkinil_v1_gpio_set_stage_ram;
*size = ARRAY_SIZE(ezkinil_bid1_gpio_set_stage_ram);
return ezkinil_bid1_gpio_set_stage_ram;
} else if (board_version == 2) {
*size = ARRAY_SIZE(ezkinil_bid2_gpio_set_stage_ram);
return ezkinil_bid2_gpio_set_stage_ram;
}
*size = 0;
return NULL;
*size = ARRAY_SIZE(ezkinil_bid3_gpio_set_stage_ram);
return ezkinil_bid3_gpio_set_stage_ram;
}

28
src/mainboard/google/zork/variants/morphius/gpio.c
View File

@ -7,20 +7,36 @@
#include <soc/gpio.h>
#include <ec/google/chromeec/ec.h>
static const struct soc_amd_gpio morphius_v1_gpio_set_stage_ram[] = {
static const struct soc_amd_gpio morphius_bid1_gpio_set_stage_ram[] = {
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* USB_OC4_L - USB_A1 */
PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
/* USB_OC2_L - USB A0 */
PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_67, HIGH),
/* DMIC_AD_EN */
PAD_GPO(GPIO_84, HIGH),
/* MST_GPIO_2 (Fw Update HDMI hub) */
PAD_GPI(GPIO_86, PULL_NONE),
/* MST_GPIO_3 (Fw Update HDMI hub) */
PAD_GPI(GPIO_90, PULL_NONE),
};
static const struct soc_amd_gpio morphius_v2_gpio_set_stage_ram[] = {
static const struct soc_amd_gpio morphius_bid2_gpio_set_stage_ram[] = {
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* USB_OC4_L - USB_A1 */
PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
/* USB_OC2_L - USB A0 */
PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_67, HIGH),
/* MST_GPIO_2 (Fw Update HDMI hub) */
PAD_GPI(GPIO_86, PULL_NONE),
/* MST_GPIO_3 (Fw Update HDMI hub) */
PAD_GPI(GPIO_90, PULL_NONE),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
@ -36,11 +52,11 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
board_version = 1;
if (board_version <= 1) {
*size = ARRAY_SIZE(morphius_v1_gpio_set_stage_ram);
return morphius_v1_gpio_set_stage_ram;
*size = ARRAY_SIZE(morphius_bid1_gpio_set_stage_ram);
return morphius_bid1_gpio_set_stage_ram;
} else if (board_version <= 2) {
*size = ARRAY_SIZE(morphius_v2_gpio_set_stage_ram);
return morphius_v2_gpio_set_stage_ram;
*size = ARRAY_SIZE(morphius_bid2_gpio_set_stage_ram);
return morphius_bid2_gpio_set_stage_ram;
}
*size = 0;

28
src/mainboard/google/zork/variants/trembyle/gpio.c
View File

@ -7,20 +7,36 @@
#include <soc/gpio.h>
#include <ec/google/chromeec/ec.h>
static const struct soc_amd_gpio trembyle_v1_v2_gpio_set_stage_ram[] = {
static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[] = {
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* USB_OC4_L - USB_A1 */
PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
/* USB_OC2_L - USB A0 */
PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_67, HIGH),
/* DMIC_AD_EN */
PAD_GPO(GPIO_84, HIGH),
/* MST_GPIO_2 (Fw Update HDMI hub) */
PAD_GPI(GPIO_86, PULL_NONE),
/* MST_GPIO_3 (Fw Update HDMI hub) */
PAD_GPI(GPIO_90, PULL_NONE),
};
static const struct soc_amd_gpio trembyle_v3_gpio_set_stage_ram[] = {
static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = {
/* DMIC_SEL */
PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
/* USB_OC4_L - USB_A1 */
PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
/* USB_OC2_L - USB A0 */
PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
/* EN_PWR_TOUCHPAD_PS2 */
PAD_GPO(GPIO_67, HIGH),
/* MST_GPIO_2 (Fw Update HDMI hub) */
PAD_GPI(GPIO_86, PULL_NONE),
/* MST_GPIO_3 (Fw Update HDMI hub) */
PAD_GPI(GPIO_90, PULL_NONE),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
@ -36,11 +52,11 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
board_version = 1;
if (board_version <= 2) {
*size = ARRAY_SIZE(trembyle_v1_v2_gpio_set_stage_ram);
return trembyle_v1_v2_gpio_set_stage_ram;
*size = ARRAY_SIZE(trembyle_bid1_bid2_gpio_set_stage_ram);
return trembyle_bid1_bid2_gpio_set_stage_ram;
} else if (board_version <= 3) {
*size = ARRAY_SIZE(trembyle_v3_gpio_set_stage_ram);
return trembyle_v3_gpio_set_stage_ram;
*size = ARRAY_SIZE(trembyle_bid3_gpio_set_stage_ram);
return trembyle_bid3_gpio_set_stage_ram;
}
*size = 0;