mb/google/zork: Update ramstage GPIOs for v3 schematics for dalboz reference

This change updates the baseboard GPIO table in ramstage to match
v3 version of dalboz reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.

BUG=b:157165628, b:157744136, b:157743835
TEST=Compiles

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If9d0e35801f9f9b15eddeb4ec7068fed6d401307
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251394
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Auto-Submit: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c

@@ -103,8 +103,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_4, PULL_UP),
 	/* PEN_POWER_EN - Enabled*/
 	PAD_GPO(GPIO_5, HIGH),
-	/* DMIC_SEL */
+	/* EN_PWR_TOUCHPAD */
-	PAD_GPO(GPIO_6, LOW), // Select Camera 1 Dmic
+	PAD_GPO(GPIO_6, HIGH),
 	/* I2S_SDIN */
 	PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
 	/* I2S_LRCLK - Bit banged in depthcharge */
@@ -134,12 +134,12 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_31, PULL_UP),
 	/*  */
 	PAD_GPI(GPIO_32, PULL_DOWN),
-	/* EN_PWR_TOUCHPAD_PS2 */
+	/* DMIC_SEL */
 	/*
-	 * EN_PWR_TOUCHPAD_PS2 - Make sure Ext ROM Sharing is disabled before
+	 * Make sure Ext ROM Sharing is disabled before using this GPIO.  Otherwise SPI flash
-	 * using this GPIO.  Otherwise SPI flash access will be very slow.
+	 * access will be very slow.
 	 */
-	PAD_GPO(GPIO_67, HIGH),
+	PAD_GPO(GPIO_67, LOW),  // Select Camera 1 Dmic
 	/* EMMC_RESET */
 	PAD_GPO(GPIO_68, LOW),
 	/* RAM ID 3*/

src/mainboard/google/zork/variants/dalboz/gpio.c

@@ -9,12 +9,23 @@
 
 /* This table is used by dalboz variant with board version < 2. */
 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
+	/* DMIC_SEL */
+	PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
 	/* USB_OC2_L - USB A0 & A1 */
 	PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
+	/* EN_PWR_TOUCHPAD_PS2 */
+	PAD_GPO(GPIO_67, HIGH),
 	/* Unused */
 	PAD_GPI(GPIO_143, PULL_DOWN),
 };
 
+static const struct soc_amd_gpio bid_2_gpio_set_stage_ram[] = {
+	/* DMIC_SEL */
+	PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
+	/* EN_PWR_TOUCHPAD_PS2 */
+	PAD_GPO(GPIO_67, HIGH),
+};
+
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
 	uint32_t board_version;
@@ -30,6 +41,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 	if (board_version < 2) {
 		*size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
 		return bid_1_gpio_set_stage_ram;
+	} else if (board_version == 2) {
+		*size = ARRAY_SIZE(bid_2_gpio_set_stage_ram);
+		return bid_2_gpio_set_stage_ram;
 	}
 
 	*size = 0;

src/mainboard/google/zork/variants/vilboz/Makefile.inc

@@ -3,3 +3,4 @@
 subdirs-y += ./spd
 
 ramstage-y += variant.c
+ramstage-y += gpio.c

src/mainboard/google/zork/variants/vilboz/gpio.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+
+/* This table is used by dalboz variant with board version < 2. */
+static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
+	/* DMIC_SEL */
+	PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
+	/* EN_PWR_TOUCHPAD_PS2 */
+	PAD_GPO(GPIO_67, HIGH),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+	uint32_t board_version;
+
+	/*
+	 * If board version cannot be read, assume that this is an older revision of the board
+	 * and so apply overrides. If board version is provided by the EC, then apply overrides
+	 * if version < 2.
+	 */
+	if (google_chromeec_cbi_get_board_version(&board_version))
+		board_version = 1;
+
+	if (board_version < 2) {
+		*size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
+		return bid_1_gpio_set_stage_ram;
+	}
+
+	*size = 0;
+	return NULL;
+}