cpu/intel/haswell: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I80b5b94b62bdd001581eb56513a0d532fffb64e8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14596 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
This commit is contained in:
Aaron Durbin
parent
309b8571cf
commit
463af337b0
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@ -193,14 +193,16 @@ void intel_cpu_haswell_finalize_smm(void);
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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/* Returns 0 on success, < 0 on failure. */
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int smm_initialize(void);
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase);
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void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size);
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void smm_initialize(void);
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void smm_relocate(void);
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struct bus;
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void bsp_init_and_start_aps(struct bus *cpu_bus);
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/* Determine if HyperThreading is disabled. The variable is not valid until
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* setup_ap_init() has been called. */
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extern int ht_disabled;
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#endif
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/* CPU identification */
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@ -714,20 +714,6 @@ static void configure_mca(void)
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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}
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static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
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{
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/* Setup MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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initialize_vr_config();
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if (haswell_is_ult()) {
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calibrate_24mhz_bclk();
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configure_pch_power_sharing();
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}
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}
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/* All CPUs including BSP will run the following function. */
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static void haswell_init(struct device *cpu)
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{
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@ -765,47 +751,27 @@ static void haswell_init(struct device *cpu)
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/* MP initialization support. */
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static const void *microcode_patch;
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int ht_disabled;
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static int ht_disabled;
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static int adjust_apic_id_ht_disabled(int index, int apic_id)
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static void pre_mp_init(void)
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{
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return 2 * index;
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/* Setup MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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initialize_vr_config();
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if (haswell_is_ult()) {
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calibrate_24mhz_bclk();
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configure_pch_power_sharing();
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}
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}
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static void relocate_and_load_microcode(void)
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static int get_cpu_count(void)
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{
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/* Relocate the SMM handler. */
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smm_relocate();
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/* After SMM relocation a 2nd microcode load is required. */
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intel_microcode_load_unlocked(microcode_patch);
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}
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static void enable_smis(void)
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{
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/* Now that all APs have been relocated as well as the BSP let SMIs
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* start flowing. */
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southbridge_smm_enable_smi();
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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static struct mp_flight_record mp_steps[] = {
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MP_FR_NOBLOCK_APS(relocate_and_load_microcode,
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relocate_and_load_microcode),
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MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
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/* Wait for APs to finish initialization before proceeding. */
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MP_FR_BLOCK_APS(NULL, enable_smis),
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};
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void bsp_init_and_start_aps(struct bus *cpu_bus)
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{
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void *smm_save_area;
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msr_t msr;
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int num_threads;
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int num_cores;
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msr_t msr;
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struct mp_params mp_params;
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msr = rdmsr(CORE_THREAD_COUNT_MSR);
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num_threads = (msr.lo >> 0) & 0xffff;
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@ -815,36 +781,60 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
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ht_disabled = num_threads == num_cores;
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/* Perform any necessary BSP initialization before APs are brought up.
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* This call also allows the BSP to prepare for any secondary effects
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* from calling cpu_initialize() such as smm_init(). */
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bsp_init_before_ap_bringup(cpu_bus);
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return num_threads;
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}
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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microcode_patch = intel_microcode_find();
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*microcode = microcode_patch;
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*parallel = 1;
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}
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/* Save default SMM area before relocation occurs. */
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smm_save_area = backup_default_smm_area();
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mp_params.num_cpus = num_threads;
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mp_params.parallel_microcode_load = 1;
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static int adjust_apic_id(int index, int apic_id)
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{
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if (ht_disabled)
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mp_params.adjust_apic_id = adjust_apic_id_ht_disabled;
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return 2 * index;
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else
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mp_params.adjust_apic_id = NULL;
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mp_params.flight_plan = &mp_steps[0];
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mp_params.num_records = ARRAY_SIZE(mp_steps);
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mp_params.microcode_pointer = microcode_patch;
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return index;
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}
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/* Load relocation and permeanent handlers. Then initiate relocation. */
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if (smm_initialize())
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printk(BIOS_CRIT, "SMM Initialiazation failed...\n");
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static void per_cpu_smm_trigger(void)
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{
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/* Relocate the SMM handler. */
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smm_relocate();
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if (mp_init(cpu_bus, &mp_params)) {
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/* After SMM relocation a 2nd microcode load is required. */
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intel_microcode_load_unlocked(microcode_patch);
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}
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static void post_mp_init(void)
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{
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/* Now that all APs have been relocated as well as the BSP let SMIs
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* start flowing. */
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southbridge_smm_enable_smi();
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = smm_info,
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.get_microcode_info = get_microcode_info,
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.adjust_cpu_apic_entry = adjust_apic_id,
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.pre_mp_smm_init = smm_initialize,
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.per_cpu_smm_trigger = per_cpu_smm_trigger,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = post_mp_init,
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};
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void bsp_init_and_start_aps(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops)) {
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printk(BIOS_ERR, "MP initialization failure.\n");
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}
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/* Restore the default SMM region. */
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restore_default_smm_area(smm_save_area);
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}
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static struct device_operations cpu_dev_ops = {
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@ -91,9 +91,9 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
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wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
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}
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static void update_save_state(int cpu,
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struct smm_relocation_params *relo_params,
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const struct smm_runtime *runtime)
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase,
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struct smm_relocation_params *relo_params)
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{
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u32 smbase;
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u32 iedbase;
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@ -101,7 +101,7 @@ static void update_save_state(int cpu,
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/* The relocated handler runs with all CPUs concurrently. Therefore
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* stagger the entry points adjusting SMBASE downwards by save state
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* size * CPU num. */
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smbase = relo_params->smram_base - cpu * runtime->save_state_size;
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smbase = staggered_smbase;
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iedbase = relo_params->ied_base;
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
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@ -132,8 +132,8 @@ static void update_save_state(int cpu,
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} else {
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em64t101_smm_state_save_area_t *save_state;
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save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
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runtime->save_state_size);
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save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
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sizeof(*save_state));
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save_state->smbase = smbase;
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save_state->iedbase = iedbase;
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@ -161,24 +161,11 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
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/* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here. */
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static void asmlinkage cpu_smm_do_relocation(void *arg)
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params;
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const struct smm_module_params *p;
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const struct smm_runtime *runtime;
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int cpu;
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p = arg;
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runtime = p->runtime;
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relo_params = p->arg;
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cpu = p->cpu;
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if (cpu >= CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Invalid CPU number assigned in SMM stub: %d\n", cpu);
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return;
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}
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struct smm_relocation_params *relo_params = &smm_reloc_params;
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
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@ -207,7 +194,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
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}
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/* Make appropriate changes to the save state map. */
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update_save_state(cpu, relo_params, runtime);
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update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
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/* Write EMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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@ -290,49 +277,6 @@ static void fill_in_relocation_params(struct device *dev,
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params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
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}
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static void adjust_apic_id_map(struct smm_loader_params *smm_params)
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{
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struct smm_runtime *runtime;
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int i;
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/* Adjust the APIC id map if HT is disabled. */
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if (!ht_disabled)
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return;
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runtime = smm_params->runtime;
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/* The APIC ids increment by 2 when HT is disabled. */
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for (i = 0; i < CONFIG_MAX_CPUS; i++)
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runtime->apic_id_to_cpu[i] = runtime->apic_id_to_cpu[i] * 2;
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}
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static int install_relocation_handler(int num_cpus,
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struct smm_relocation_params *relo_params)
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{
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/* The default SMM entry can happen in parallel or serially. If the
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* default SMM entry is done in parallel the BSP has already setup
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* the saving state to each CPU's MSRs. At least one save state size
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* is required for the initial SMM entry for the BSP to determine if
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* parallel SMM relocation is even feasible. Set the stack size to
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* the save state size, and call into the do_relocation handler. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = 1,
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.handler = (smm_handler_t)&cpu_smm_do_relocation,
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.handler_arg = (void *)relo_params,
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};
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if (smm_setup_relocation_handler(&smm_params))
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return -1;
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adjust_apic_id_map(&smm_params);
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return 0;
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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{
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char *ied_base;
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@ -357,88 +301,43 @@ static void setup_ied_area(struct smm_relocation_params *params)
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//memset(ied_base + (2 << 20), 0, (2 << 20));
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}
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static int install_permanent_handler(int num_cpus,
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struct smm_relocation_params *relo_params)
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void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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/* There are num_cpus concurrent stacks and num_cpus concurrent save
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* state areas. Lastly, set the stack size to the save state size. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = num_cpus,
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};
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printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
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relo_params->smram_base);
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if (smm_load_module((void *)relo_params->smram_base,
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relo_params->smram_size, &smm_params))
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return -1;
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adjust_apic_id_map(&smm_params);
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return 0;
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}
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static int cpu_smm_setup(void)
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{
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struct device *dev;
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int num_cpus;
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msr_t msr;
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device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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fill_in_relocation_params(dev, &smm_reloc_params);
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setup_ied_area(&smm_reloc_params);
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msr = rdmsr(CORE_THREAD_COUNT_MSR);
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num_cpus = msr.lo & 0xffff;
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if (num_cpus > CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
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num_cpus, CONFIG_MAX_CPUS);
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}
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if (install_relocation_handler(num_cpus, &smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Relocation handler install failed.\n");
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return -1;
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}
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if (install_permanent_handler(num_cpus, &smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Permanent handler install failed.\n");
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return -1;
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}
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/* Ensure the SMM handlers hit DRAM before performing first SMI. */
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/* TODO(adurbin): Is this really needed? */
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wbinvd();
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return 0;
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*perm_smbase = smm_reloc_params.smram_base;
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*perm_smsize = smm_reloc_params.smram_size;
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*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
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}
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int smm_initialize(void)
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void smm_initialize(void)
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{
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/* Return early if CPU SMM setup failed. */
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if (cpu_smm_setup())
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return -1;
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/* Clear the SMM state in the southbridge. */
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southbridge_smm_clear_state();
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/* Run the relocation handler. */
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/*
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* Run the relocation handler for on the BSP to check and set up
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* parallel SMM relocation.
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*/
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smm_initiate_relocation();
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if (smm_reloc_params.smm_save_state_in_msrs) {
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printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
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}
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return 0;
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}
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/* The default SMM entry can happen in parallel or serially. If the
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* default SMM entry is done in parallel the BSP has already setup
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* the saving state to each CPU's MSRs. At least one save state size
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* is required for the initial SMM entry for the BSP to determine if
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* parallel SMM relocation is even feasible. */
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void smm_relocate(void)
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{
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/*
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