Drop SC520 and related boards
There is no Cache As Ram for these boards, let's get rid of them. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ia70befc59708c360ad02ed7e3a49d3b0f95dc707 Reviewed-on: http://review.coreboot.org/7119 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Stefan Reinauer
parent
bfea6cc2e0
commit
46c85d7dfb
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@ -15,7 +15,5 @@ source src/cpu/amd/model_10xxx/Kconfig
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source src/cpu/amd/geode_gx2/Kconfig
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source src/cpu/amd/geode_gx2/Kconfig
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source src/cpu/amd/geode_lx/Kconfig
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source src/cpu/amd/geode_lx/Kconfig
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source src/cpu/amd/sc520/Kconfig
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source src/cpu/amd/agesa/Kconfig
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source src/cpu/amd/agesa/Kconfig
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source src/cpu/amd/pi/Kconfig
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source src/cpu/amd/pi/Kconfig
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@ -10,7 +10,6 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
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subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
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subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
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subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
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subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
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subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
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subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
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subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
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subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
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subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
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subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
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@ -1,5 +0,0 @@
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config CPU_AMD_SC520
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bool
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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@ -1 +0,0 @@
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ramstage-y += sc520.c
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@ -1,643 +0,0 @@
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/* this setupcpu function comes from: */
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/*==============================================================================*/
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/* FILE : start16.asm*/
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/**/
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/* DESC : A 16 bit mode assembly language startup program, intended for*/
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/* use with on Aspen SC520 platforms.*/
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/**/
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/* 11/16/2000 Added support for the NetSC520*/
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/* 12/28/2000 Modified to boot linux image*/
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/**/
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/* =============================================================================*/
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/* */
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/* Copyright 2000 Advanced Micro Devices, Inc. */
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/* */
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/* This software is the property of Advanced Micro Devices, Inc (AMD) which */
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/* specifically grants the user the right to modify, use and distribute this */
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/* software provided this COPYRIGHT NOTICE is not removed or altered. All */
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/* other rights are reserved by AMD. */
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/* */
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/* THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY */
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/* OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF */
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/* THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.*/
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/* IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER*/
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/* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS*/
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/* INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY*/
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/* TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF*/
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/* SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR*/
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/* LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE*/
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/* LIMITATION MAY NOT APPLY TO YOU.*/
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/**/
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/* AMD does not assume any responsibility for any errors that may appear in*/
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/* the Materials nor any responsibility to support or update the Materials.*/
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/* AMD retains the right to make changes to its test specifications at any*/
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/* time, without notice.*/
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/**/
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/* So that all may benefit from your experience, please report any problems */
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/* or suggestions about this software back to AMD. Please include your name, */
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/* company, telephone number, AMD product requiring support and question or */
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/* problem encountered. */
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/* */
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/* Advanced Micro Devices, Inc. Worldwide support and contact */
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/* Embedded Processor Division information available at: */
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/* Systems Engineering epd.support@amd.com*/
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/* 5204 E. Ben White Blvd. -or-*/
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/* Austin, TX 78741 http://www.amd.com/html/support/techsup.html*/
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/* ============================================================================*/
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#define OUTC(addr, val) *(unsigned char *)(addr) = (val)
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/* sadly, romcc can't quite handle what we want, so we do this ugly thing */
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#define drcctl (( volatile unsigned char *)0xfffef010)
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#define drcmctl (( volatile unsigned char *)0xfffef012)
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#define drccfg (( volatile unsigned char *)0xfffef014)
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#define drcbendadr (( volatile unsigned long *)0xfffef018)
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#define eccctl (( volatile unsigned char *)0xfffef020)
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#define dbctl (( volatile unsigned char *)0xfffef040)
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void setupsc520(void)
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{
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volatile unsigned char *cp;
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volatile unsigned short *sp;
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volatile unsigned long *edi;
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/* do this to see if MMCR will start acting right. we suspect
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* you have to do SOMETHING to get things going. I'm really
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* starting to hate this processor.
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*/
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/* no, that did not help. I wonder what will?
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* outl(0x800df0cb, 0xfffc);
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*/
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/* well, this is special! You have to do SHORT writes to the
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* locations, even though they are CHAR in size and CHAR aligned
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* and technically, a SHORT write will result in -- yoo ha! --
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* over writing the next location! Thanks to the u-boot guys
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* for a reference code I can use. with these short pointers,
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* it now reliably comes up after power cycle with printk. Ah yi
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* yi.
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*/
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/* turn off the write buffer*/
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/* per the note above, make this a short? Let's try it. */
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sp = (unsigned short *)0xfffef040;
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*sp = 0;
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/* as per the book: */
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/* PAR register setup */
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/* set up the PAR registers as they are on the MSM586SEG */
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/* moved to romstage.c by Stepan, Ron says: */
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/* NOTE: move this to mainboard.c ASAP */
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setup_pars();
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/* CPCSF register */
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sp = (unsigned short *)0xfffefc24;
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*sp = 0xfe;
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/* ADDDECTL */
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sp = (unsigned short *)0xfffefc80;
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*sp = 0x10;
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/* byte writes in AMD assembly */
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/* we do short anyway, since u-boot does ... */
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/*set the GP CS offset*/
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sp = (unsigned short *)0xfffefc08;
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*sp = 0x00001;
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/*set the GP CS width*/
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sp = (unsigned short *)0xfffefc09;
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*sp = 0x00003;
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/* short writes in AMD assembly */
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/*set the GP CS width*/
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sp = (unsigned short *)0xfffefc0a;
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*sp = 0x00001;
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/*set the RD pulse width*/
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sp = (unsigned short *)0xfffefc0b;
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*sp = 0x00003;
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/*set the GP RD offset */
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sp = (unsigned short *)0xfffefc0c;
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*sp = 0x00001;
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/*set the GP WR pulse width*/
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sp = (unsigned short *)0xfffefc0d;
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*sp = 0x00003;
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/*set the GP WR offset*/
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sp = (unsigned short *)0xfffefc0e;
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*sp = 0x00001;
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/* set up the GP IO pins*/
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/*set the GPIO directionreg*/
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sp = (unsigned short *)0xfffefc2c;
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*sp = 0x00000;
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/*set the GPIO directionreg*/
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sp = (unsigned short *)0xfffefc2a;
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*sp = 0x00000;
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/*set the GPIO pin function 31-16 reg*/
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sp = (unsigned short *)0xfffefc22;
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*sp = 0x0FFFF;
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/*set the GPIO pin function 15-0 reg*/
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sp = (unsigned short *)0xfffefc20;
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*sp = 0x0FFFF;
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/* the 0x80 led should now be working*/
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post_code(0xaa);
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#if 0
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/* wtf are 680 leds ... *//* <-- WTF is this comment? */
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par = (unsigned long *) 0xfffef0c4;
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*par = 0x28000680;
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/* well? */
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post_code(0x55);
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#endif
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/* set the uart baud rate clocks to the normal 1.8432 MHz.*/
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/* enable interrupts here? Why not? */
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cp = (unsigned char *)0xfffefcc0;
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*cp = 4 | 3; /* uart 1 clock source */
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cp = (unsigned char *)0xfffefcc4;
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*cp = 4; /* uart 2 clock source */
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#if 0
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/*; set the interrupt mapping registers.*/
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cp = (unsigned char *)0x0fffefd20;
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*cp = 0x01;
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cp = (unsigned char *)0x0fffefd28;
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*cp = 0x0c;
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cp = (unsigned char *)0x0fffefd29;
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*cp = 0x0b;
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cp = (unsigned char *)0x0fffefd30;
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*cp = 0x07;
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cp = (unsigned char *)0x0fffefd43;
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*cp = 0x03;
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cp = (unsigned char *)0x0fffefd51;
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*cp = 0x02;
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#endif
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/* Stepan says: This needs to go to the msm586seg code */
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/* "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
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outl(0x08000683c, 0xcf8);
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outl(0xc, 0xcfc); /* set the interrupt line */
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/* Set the SC520 PCI host bridge to target mode to
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* allow external bus mastering events
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*/
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/* index the status command register on device 0*/
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outl(0x080000004, 0x0cf8);
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outl(0x2, 0xcfc); /*set the memory access enable bit*/
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OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
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}
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/*
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*
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*
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*/
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#define CACHELINESZ 0x00000010 /* size of our cache line (read buffer)*/
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#define COL11_ADR *(unsigned int *)0x0e001e00 /* 11 col addrs*/
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#define COL10_ADR *(unsigned int *)0x0e000e00 /* 10 col addrs*/
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#define COL09_ADR *(unsigned int *)0x0e000600 /* 9 col addrs*/
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#define COL08_ADR *(unsigned int *)0x0e000200 /* 8 col addrs*/
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#define ROW14_ADR *(unsigned int *)0x0f000000 /* 14 row addrs*/
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#define ROW13_ADR *(unsigned int *)0x07000000 /* 13 row addrs*/
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#define ROW12_ADR *(unsigned int *)0x03000000 /* 12 row addrs*/
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#define ROW11_ADR *(unsigned int *)0x01000000 /* 11 row addrs/also bank switch*/
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#define ROW10_ADR *(unsigned int *)0x00000000 /* 10 row addrs/also bank switch*/
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#define COL11_DATA 0x0b0b0b0b /* 11 col addrs*/
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#define COL10_DATA 0x0a0a0a0a /* 10 col data*/
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#define COL09_DATA 0x09090909 /* 9 col data*/
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#define COL08_DATA 0x08080808 /* 8 col data*/
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#define ROW14_DATA 0x3f3f3f3f /* 14 row data (MASK)*/
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#define ROW13_DATA 0x1f1f1f1f /* 13 row data (MASK)*/
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#define ROW12_DATA 0x0f0f0f0f /* 12 row data (MASK)*/
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#define ROW11_DATA 0x07070707 /* 11 row data/also bank switch (MASK)*/
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#define ROW10_DATA 0xaaaaaaaa /* 10 row data/also bank switch (MASK)*/
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void
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dummy_write(void){
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volatile unsigned short *ptr = (volatile unsigned short *)CACHELINESZ;
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*ptr = 0;
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}
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#include "drivers/pc80/udelay_io.c"
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static void dumpram(void){
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print_err("ctl "); print_err_hex8(*drcctl); print_err("\n");
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print_err("mctl "); print_err_hex8(*drcmctl); print_err("\n");
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print_err("cfg "); print_err_hex8(*drccfg); print_err("\n");
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print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\n");
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print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\n");
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print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\n");
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print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
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}
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/* there is a lot of silliness in the amd code, and it is
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* causing romcc real headaches, so we're going to be be a little
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* less silly.
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* so, the order of ops is:
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* for i in 3 to 0
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* see if bank is there.
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* if we can write a word, and read it back, to hell with paranoia
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* the bank is there. So write the magic byte, read it back, and
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* use that to get size, etc. Try to keep things very simple,
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* so people can actually follow the damned code.
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*/
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/* cache is assumed to be disabled */
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int sizemem(void)
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{
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int rows,banks, cols, i, bank;
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unsigned char al;
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volatile unsigned long *lp = (volatile unsigned long *) CACHELINESZ;
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unsigned long l;
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/* initialize dram controller registers */
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/* disable write buffer/read-ahead buffer */
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*dbctl = 0;
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/* no ecc interrupts of any kind. */
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*eccctl = 0;
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/* Set SDRAM timing for slowest speed. */
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*drcmctl = 0x1e;
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/* setup dram register for all banks
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* with max cols and max banks
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* this is the oldest trick in the book. You are going to set up for max rows
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* and cols, then do a write, then see if the data is wrapped to low memory.
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* you can actually tell by which data gets to which low memory,
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* exactly how many rows and cols you have.
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*/
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*drccfg=0xbbbb;
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/* setup loop to do 4 external banks starting with bank 3 */
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*drcbendadr=0x0ff000000;
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/* for now, set it up for one loop of bank 0. Just to get it to go at all. */
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*drcbendadr=0x0ff;
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/* issue a NOP to all DRAMs */
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/* Setup DRAM control register with Disable refresh,
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* disable write buffer Test Mode and NOP command select
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*/
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*drcctl=0x01;
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/* dummy write for NOP to take effect */
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dummy_write();
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print_err("NOP\n");
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/* 100? 200? */
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udelay(100);
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print_err("after udelay\n");
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/* issue all banks precharge */
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*drcctl=0x02;
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print_err("set *drcctl to 2 \n");
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dummy_write();
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print_err("PRE\n");
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/* issue 2 auto refreshes to all banks */
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*drcctl=0x04;
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dummy_write();
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print_err("AUTO1\n");
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dummy_write();
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print_err("AUTO2\n");
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/* issue LOAD MODE REGISTER command */
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*drcctl=0x03;
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|
||||||
dummy_write();
|
|
||||||
print_err("LOAD MODE REG\n");
|
|
||||||
|
|
||||||
*drcctl=0x04;
|
|
||||||
for (i=0; i<8; i++) /* refresh 8 times */{
|
|
||||||
dummy_write();
|
|
||||||
print_err("dummy write\n");
|
|
||||||
}
|
|
||||||
print_err("8 dummy writes\n");
|
|
||||||
|
|
||||||
/* set control register to NORMAL mode */
|
|
||||||
*drcctl=0x00;
|
|
||||||
print_err("normal\n");
|
|
||||||
|
|
||||||
print_err("HI done normal\n");
|
|
||||||
|
|
||||||
print_err("sizemem\n");
|
|
||||||
for(bank = 3; bank >= 0; bank--) {
|
|
||||||
print_err("Try to assign to l\n");
|
|
||||||
*lp = 0xdeadbeef;
|
|
||||||
print_err("assigned l ... \n");
|
|
||||||
if (*lp != 0xdeadbeef) {
|
|
||||||
print_err(" no memory at bank ");
|
|
||||||
// print_err_hex8(bank);
|
|
||||||
// print_err(" value "); print_err_hex32(*lp);
|
|
||||||
print_err("\n");
|
|
||||||
// continue;
|
|
||||||
}
|
|
||||||
*drcctl = 2;
|
|
||||||
dummy_write();
|
|
||||||
*drccfg = *drccfg >> 4;
|
|
||||||
l = *drcbendadr;
|
|
||||||
l >>= 8;
|
|
||||||
*drcbendadr = l;
|
|
||||||
print_err("loop around\n");
|
|
||||||
*drcctl = 0;
|
|
||||||
dummy_write();
|
|
||||||
}
|
|
||||||
#if 0
|
|
||||||
/* enable last bank and setup ending address
|
|
||||||
* register for max ram in last bank
|
|
||||||
*/
|
|
||||||
*drcbendadr=0x0ff000000;
|
|
||||||
|
|
||||||
|
|
||||||
// dumpram();
|
|
||||||
|
|
||||||
/* issue a NOP to all DRAMs */
|
|
||||||
/* Setup DRAM control register with Disable refresh,
|
|
||||||
* disable write buffer Test Mode and NOP command select
|
|
||||||
*/
|
|
||||||
*drcctl=0x01;
|
|
||||||
|
|
||||||
/* dummy write for NOP to take effect */
|
|
||||||
dummy_write();
|
|
||||||
print_err("NOP\n");
|
|
||||||
/* 100? 200? */
|
|
||||||
//udelay(100);
|
|
||||||
print_err("after udelay\n");
|
|
||||||
|
|
||||||
/* issue all banks precharge */
|
|
||||||
*drcctl=0x02;
|
|
||||||
print_err("set *drcctl to 2 \n");
|
|
||||||
dummy_write();
|
|
||||||
print_err("PRE\n");
|
|
||||||
|
|
||||||
/* issue 2 auto refreshes to all banks */
|
|
||||||
*drcctl=0x04;
|
|
||||||
dummy_write();
|
|
||||||
print_err("AUTO1\n");
|
|
||||||
dummy_write();
|
|
||||||
print_err("AUTO2\n");
|
|
||||||
|
|
||||||
/* issue LOAD MODE REGISTER command */
|
|
||||||
*drcctl=0x03;
|
|
||||||
dummy_write();
|
|
||||||
print_err("LOAD MODE REG\n");
|
|
||||||
|
|
||||||
*drcctl=0x04;
|
|
||||||
for (i=0; i<8; i++) /* refresh 8 times */{
|
|
||||||
dummy_write();
|
|
||||||
print_err("dummy write\n");
|
|
||||||
}
|
|
||||||
print_err("8 dummy writes\n");
|
|
||||||
|
|
||||||
/* set control register to NORMAL mode */
|
|
||||||
*drcctl=0x00;
|
|
||||||
print_err("normal\n");
|
|
||||||
|
|
||||||
print_err("HI done normal\n");
|
|
||||||
bank = 3;
|
|
||||||
|
|
||||||
|
|
||||||
/* this is really ugly, it is right from assembly code.
|
|
||||||
* we need to clean it up later
|
|
||||||
*/
|
|
||||||
|
|
||||||
start:
|
|
||||||
/* write col 11 wrap adr */
|
|
||||||
COL11_ADR=COL11_DATA;
|
|
||||||
if(COL11_ADR!=COL11_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
|
|
||||||
print_err("11\n");
|
|
||||||
/* write col 10 wrap adr */
|
|
||||||
COL10_ADR=COL10_DATA;
|
|
||||||
if(COL10_ADR!=COL10_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("10\n");
|
|
||||||
|
|
||||||
/* write col 9 wrap adr */
|
|
||||||
COL09_ADR=COL09_DATA;
|
|
||||||
if(COL09_ADR!=COL09_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("9\n");
|
|
||||||
|
|
||||||
/* write col 8 wrap adr */
|
|
||||||
COL08_ADR=COL08_DATA;
|
|
||||||
if(COL08_ADR!=COL08_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("8\n");
|
|
||||||
|
|
||||||
/* write row 14 wrap adr */
|
|
||||||
ROW14_ADR=ROW14_DATA;
|
|
||||||
if(ROW14_ADR!=ROW14_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("14\n");
|
|
||||||
|
|
||||||
/* write row 13 wrap adr */
|
|
||||||
ROW13_ADR=ROW13_DATA;
|
|
||||||
if(ROW13_ADR!=ROW13_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("13\n");
|
|
||||||
|
|
||||||
/* write row 12 wrap adr */
|
|
||||||
ROW12_ADR=ROW12_DATA;
|
|
||||||
if(ROW12_ADR!=ROW12_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("12\n");
|
|
||||||
|
|
||||||
/* write row 11 wrap adr */
|
|
||||||
ROW11_ADR=ROW11_DATA;
|
|
||||||
if(ROW11_ADR!=ROW11_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("11\n");
|
|
||||||
|
|
||||||
/* write row 10 wrap adr */
|
|
||||||
ROW10_ADR=ROW10_DATA;
|
|
||||||
if(ROW10_ADR!=ROW10_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
print_err("10\n");
|
|
||||||
|
|
||||||
/*
|
|
||||||
* read data @ row 12 wrap adr to determine # banks,
|
|
||||||
* and read data @ row 14 wrap adr to determine # rows.
|
|
||||||
* if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
|
|
||||||
* if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
|
|
||||||
* if data @ row 12 wrap == 11 or 12, we have 4 banks
|
|
||||||
*/
|
|
||||||
|
|
||||||
banks=2;
|
|
||||||
if (ROW12_ADR != ROW10_DATA) {
|
|
||||||
banks=4;
|
|
||||||
print_err("4b\n");
|
|
||||||
if(ROW12_ADR != ROW11_DATA) {
|
|
||||||
if(ROW12_ADR != ROW12_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* validate row mask */
|
|
||||||
rows=ROW14_ADR;
|
|
||||||
if (rows<ROW11_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
if (rows>ROW14_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
/* verify all 4 bytes of dword same */
|
|
||||||
/*
|
|
||||||
if(rows&0xffff!=(rows>>16)&0xffff)
|
|
||||||
goto bad_ram;
|
|
||||||
if(rows&0xff!=(rows>>8)&0xff)
|
|
||||||
goto bad_ram;
|
|
||||||
*/
|
|
||||||
/* now just get one of them */
|
|
||||||
rows &= 0xff;
|
|
||||||
print_err("rows"); print_err_hex32(rows); print_err("\n");
|
|
||||||
/* validate column data */
|
|
||||||
cols=COL11_ADR;
|
|
||||||
if(cols<COL08_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
if (cols>COL11_DATA)
|
|
||||||
goto bad_ram;
|
|
||||||
/* verify all 4 bytes of dword same */
|
|
||||||
/*
|
|
||||||
if(cols&0xffff!=(cols>>16)&0xffff)
|
|
||||||
goto bad_ram;
|
|
||||||
if(cols&0xff!=(cols>>8)&0xff)
|
|
||||||
goto bad_ram;
|
|
||||||
*/
|
|
||||||
print_err("cols"); print_err_hex32(cols); print_err("\n");
|
|
||||||
cols -= COL08_DATA;
|
|
||||||
|
|
||||||
/* cols now is in the range of 0 1 2 3 ...
|
|
||||||
*/
|
|
||||||
i = cols&3;
|
|
||||||
// i = cols + rows;
|
|
||||||
|
|
||||||
/* wacky end addr calculation */
|
|
||||||
/*
|
|
||||||
al = 3;
|
|
||||||
al -= (i & 0xff);k
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* what a fookin' mess this is */
|
|
||||||
if(banks==4)
|
|
||||||
i+=8; /* <-- i holds merged value */
|
|
||||||
/* i now has the col width in bits 0-1 and the bank count (2 or 4)
|
|
||||||
* in bit 3.
|
|
||||||
* this is the format for the drccfg register
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* fix ending addr mask*/
|
|
||||||
/*FIXME*/
|
|
||||||
/* let's just go with this to start ... see if we can get ANYWHERE */
|
|
||||||
/* need to get end addr. Need to do it with the bank in mind. */
|
|
||||||
/*
|
|
||||||
al = 3;
|
|
||||||
al -= i&3;
|
|
||||||
*drcbendaddr = rows >> al;
|
|
||||||
print_err("computed ending_adr = "); print_err_hex8(ending_adr);
|
|
||||||
print_err("\n");
|
|
||||||
|
|
||||||
*/
|
|
||||||
bad_reinit:
|
|
||||||
/* issue all banks recharge */
|
|
||||||
*drcctl=0x02;
|
|
||||||
dummy_write();
|
|
||||||
|
|
||||||
/* update ending address register */
|
|
||||||
// *drcbendadr = ending_adr;
|
|
||||||
|
|
||||||
/* update config register */
|
|
||||||
*drccfg &= ~(0xff << bank*4);
|
|
||||||
if (ending_adr)
|
|
||||||
*drccfg = ((banks == 4 ? 8 : 0) | cols & 3)<< (bank*4);
|
|
||||||
// dumpram();
|
|
||||||
/* skip the rest for now */
|
|
||||||
// bank = 0;
|
|
||||||
// *drccfg=*drccfg&YYY|ZZZZ;
|
|
||||||
|
|
||||||
if(bank!=0) {
|
|
||||||
bank--;
|
|
||||||
// drcbendaddr--;
|
|
||||||
*drcbendaddr = 0xff000000;
|
|
||||||
//*(&*drcbendadr+XXYYXX)=0xff;
|
|
||||||
goto start;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* set control register to NORMAL mode */
|
|
||||||
*drcctl=0x18;
|
|
||||||
dummy_write();
|
|
||||||
return bank;
|
|
||||||
|
|
||||||
bad_ram:
|
|
||||||
print_info("bad ram!\n");
|
|
||||||
/* you are here because the read-after-write failed,
|
|
||||||
* in most cases because: no ram in that bank!
|
|
||||||
* set badbank to 1 and go to reinit
|
|
||||||
*/
|
|
||||||
ending_adr = 0;
|
|
||||||
goto bad_reinit;
|
|
||||||
while(1)
|
|
||||||
print_err("DONE NEXTBANK\n");
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/* note: based on AMD code*/
|
|
||||||
/* This code is known to work on the digital logic board and on the technologic
|
|
||||||
* systems ts5300
|
|
||||||
*/
|
|
||||||
int staticmem(void)
|
|
||||||
{
|
|
||||||
volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
|
|
||||||
|
|
||||||
/* set up 0x18 .. **/
|
|
||||||
*drcbendadr = 0x88;
|
|
||||||
*drcmctl = 0x1e;
|
|
||||||
*drccfg = 0x9;
|
|
||||||
/* nop mode */
|
|
||||||
*drcctl = 0x1;
|
|
||||||
/* do the dummy write */
|
|
||||||
*zero = 0;
|
|
||||||
|
|
||||||
/* precharge */
|
|
||||||
*drcctl = 2;
|
|
||||||
*zero = 0;
|
|
||||||
|
|
||||||
/* two autorefreshes */
|
|
||||||
*drcctl = 4;
|
|
||||||
*zero = 0;
|
|
||||||
print_debug("one zero out on refresh\n");
|
|
||||||
*zero = 0;
|
|
||||||
print_debug("two zero out on refresh\n");
|
|
||||||
|
|
||||||
/* load mode register */
|
|
||||||
*drcctl = 3;
|
|
||||||
*zero = 0;
|
|
||||||
print_debug("DONE the load mode reg\n");
|
|
||||||
|
|
||||||
/* normal mode */
|
|
||||||
*drcctl = 0x0;
|
|
||||||
*zero = 0;
|
|
||||||
print_debug("DONE one last write and then turn on refresh etc\n");
|
|
||||||
*drcctl = 0x18;
|
|
||||||
*zero = 0;
|
|
||||||
print_debug("DONE the normal\n");
|
|
||||||
*zero = 0xdeadbeef;
|
|
||||||
if (*zero != 0xdeadbeef)
|
|
||||||
print_debug("NO LUCK\n");
|
|
||||||
else
|
|
||||||
print_debug("did a store and load ...\n");
|
|
||||||
//print_err_hex32(*zero);
|
|
||||||
// print_err(" zero is now "); print_err_hex32(*zero); print_err("\n");
|
|
||||||
}
|
|
||||||
|
|
@ -1,200 +0,0 @@
|
||||||
/*
|
|
||||||
* This file needs a major cleanup. Too much #if 0 code
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include <arch/ioapic.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/hypertransport.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <delay.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* set up basic things ...
|
|
||||||
* PAR should NOT go here, as it might change with the mainboard.
|
|
||||||
*/
|
|
||||||
static void cpu_init(device_t dev)
|
|
||||||
{
|
|
||||||
unsigned long *l = (unsigned long *) 0xfffef088;
|
|
||||||
int i;
|
|
||||||
for(i = 0; i < 16; i++, l++)
|
|
||||||
printk(BIOS_ERR, "Par%d: 0x%lx\n", i, *l);
|
|
||||||
|
|
||||||
printk(BIOS_SPEW, "SC520 random fixup ...\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/* Ollie says: make a northbridge/amd/sc520. Ron sez:
|
|
||||||
* there is no real northbridge, keep it here in cpu.
|
|
||||||
* Ron wins, he's writing the code.
|
|
||||||
*/
|
|
||||||
static void sc520_enable_resources(struct device *dev) {
|
|
||||||
unsigned char command;
|
|
||||||
|
|
||||||
printk(BIOS_SPEW, "%s\n", __func__);
|
|
||||||
command = pci_read_config8(dev, PCI_COMMAND);
|
|
||||||
printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
|
|
||||||
command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
|
|
||||||
printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
|
|
||||||
pci_write_config8(dev, PCI_COMMAND, command);
|
|
||||||
command = pci_read_config8(dev, PCI_COMMAND);
|
|
||||||
printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void sc520_read_resources(device_t dev)
|
|
||||||
{
|
|
||||||
struct resource* res;
|
|
||||||
|
|
||||||
pci_dev_read_resources(dev);
|
|
||||||
|
|
||||||
res = new_resource(dev, 1);
|
|
||||||
res->base = 0x0UL;
|
|
||||||
res->size = 0x400UL;
|
|
||||||
res->limit = 0xffffUL;
|
|
||||||
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
||||||
|
|
||||||
res = new_resource(dev, 3); /* IOAPIC */
|
|
||||||
res->base = IO_APIC_ADDR;
|
|
||||||
res->size = 0x00001000;
|
|
||||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static struct device_operations cpu_operations = {
|
|
||||||
.read_resources = sc520_read_resources,
|
|
||||||
.set_resources = pci_dev_set_resources,
|
|
||||||
.enable_resources = sc520_enable_resources,
|
|
||||||
.init = cpu_init,
|
|
||||||
.enable = 0,
|
|
||||||
.ops_pci = 0,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct pci_driver cpu_driver __pci_driver = {
|
|
||||||
.ops = &cpu_operations,
|
|
||||||
.vendor = PCI_VENDOR_ID_AMD,
|
|
||||||
.device = 0x3000
|
|
||||||
};
|
|
||||||
|
|
||||||
static void pci_domain_set_resources(device_t dev)
|
|
||||||
{
|
|
||||||
device_t mc_dev;
|
|
||||||
uint32_t pci_tolm;
|
|
||||||
printk(BIOS_SPEW, "%s\n", __func__);
|
|
||||||
pci_tolm = find_pci_tolm(dev->link_list);
|
|
||||||
mc_dev = dev->link_list->children;
|
|
||||||
if (mc_dev) {
|
|
||||||
unsigned long tomk, tolmk;
|
|
||||||
// unsigned char rambits;
|
|
||||||
// int i;
|
|
||||||
int idx;
|
|
||||||
#if 0
|
|
||||||
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
|
|
||||||
unsigned char reg;
|
|
||||||
reg = pci_read_config8(mc_dev, ramregs[i]);
|
|
||||||
/* these are ENDING addresses, not sizes.
|
|
||||||
* if there is memory in this slot, then reg will be > rambits.
|
|
||||||
* So we just take the max, that gives us total.
|
|
||||||
* We take the highest one to cover for once and future coreboot
|
|
||||||
* bugs. We warn about bugs.
|
|
||||||
*/
|
|
||||||
if (reg > rambits)
|
|
||||||
rambits = reg;
|
|
||||||
if (reg < rambits)
|
|
||||||
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
|
|
||||||
ramregs[i]);
|
|
||||||
}
|
|
||||||
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
|
|
||||||
tomk = rambits*8*1024;
|
|
||||||
#endif
|
|
||||||
tomk = 32 * 1024;
|
|
||||||
/* Compute the top of Low memory */
|
|
||||||
tolmk = pci_tolm >> 10;
|
|
||||||
if (tolmk >= tomk) {
|
|
||||||
/* The PCI hole does does not overlap the memory.
|
|
||||||
*/
|
|
||||||
tolmk = tomk;
|
|
||||||
}
|
|
||||||
/* Report the memory regions */
|
|
||||||
idx = 10;
|
|
||||||
ram_resource(dev, idx++, 0, tolmk);
|
|
||||||
}
|
|
||||||
assign_resources(dev->link_list);
|
|
||||||
}
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
void sc520_enable_resources(device_t dev) {
|
|
||||||
|
|
||||||
printk(BIOS_SPEW, "%s\n", __func__);
|
|
||||||
printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n");
|
|
||||||
|
|
||||||
/*
|
|
||||||
command = pci_read_config8(dev, PCI_COMMAND);
|
|
||||||
printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
|
|
||||||
command |= PCI_COMMAND_MEMORY;
|
|
||||||
printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
|
|
||||||
pci_write_config8(dev, PCI_COMMAND, command);
|
|
||||||
command = pci_read_config8(dev, PCI_COMMAND);
|
|
||||||
printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
|
|
||||||
*/
|
|
||||||
enable_childrens_resources(dev);
|
|
||||||
printk(BIOS_SPEW, "%s\n", __func__);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static struct device_operations pci_domain_ops = {
|
|
||||||
.read_resources = pci_domain_read_resources,
|
|
||||||
.set_resources = pci_domain_set_resources,
|
|
||||||
/*
|
|
||||||
* If enable_resources is set to the generic enable_resources
|
|
||||||
* function the whole thing will hang in an endless loop on
|
|
||||||
* the ts5300. If this is really needed on another platform,
|
|
||||||
* something is conceptually wrong.
|
|
||||||
*/
|
|
||||||
.enable_resources = 0, //enable_resources,
|
|
||||||
.init = 0,
|
|
||||||
.scan_bus = pci_domain_scan_bus,
|
|
||||||
.ops_pci_bus = pci_bus_default_ops,
|
|
||||||
};
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
static void cpu_bus_init(device_t dev)
|
|
||||||
{
|
|
||||||
printk(BIOS_SPEW, "cpu_bus_init\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct device_operations cpu_bus_ops = {
|
|
||||||
.read_resources = DEVICE_NOOP,
|
|
||||||
.set_resources = DEVICE_NOOP,
|
|
||||||
.enable_resources = DEVICE_NOOP,
|
|
||||||
.init = cpu_bus_init,
|
|
||||||
.scan_bus = 0,
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static void enable_dev(struct device *dev)
|
|
||||||
{
|
|
||||||
printk(BIOS_SPEW, "%s\n", __func__);
|
|
||||||
/* Set the operations if it is a special bus type */
|
|
||||||
if (dev->path.type == DEVICE_PATH_DOMAIN) {
|
|
||||||
dev->ops = &pci_domain_ops;
|
|
||||||
}
|
|
||||||
#if 0
|
|
||||||
/* This is never hit as none of the sc520 boards have
|
|
||||||
* an APIC cluster defined
|
|
||||||
*/
|
|
||||||
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
|
|
||||||
dev->ops = &cpu_bus_ops;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
struct chip_operations cpu_amd_sc520_ops = {
|
|
||||||
CHIP_NAME("AMD Elan SC520 CPU")
|
|
||||||
.enable_dev = enable_dev,
|
|
||||||
};
|
|
||||||
|
|
@ -120,8 +120,6 @@ config VENDOR_SUPERMICRO
|
||||||
bool "Supermicro"
|
bool "Supermicro"
|
||||||
config VENDOR_TECHNEXION
|
config VENDOR_TECHNEXION
|
||||||
bool "Technexion"
|
bool "Technexion"
|
||||||
config VENDOR_TECHNOLOGIC
|
|
||||||
bool "Technologic"
|
|
||||||
config VENDOR_TI
|
config VENDOR_TI
|
||||||
bool "TI"
|
bool "TI"
|
||||||
config VENDOR_THOMSON
|
config VENDOR_THOMSON
|
||||||
|
|
@ -197,7 +195,6 @@ source "src/mainboard/soyo/Kconfig"
|
||||||
source "src/mainboard/sunw/Kconfig"
|
source "src/mainboard/sunw/Kconfig"
|
||||||
source "src/mainboard/supermicro/Kconfig"
|
source "src/mainboard/supermicro/Kconfig"
|
||||||
source "src/mainboard/technexion/Kconfig"
|
source "src/mainboard/technexion/Kconfig"
|
||||||
source "src/mainboard/technologic/Kconfig"
|
|
||||||
source "src/mainboard/thomson/Kconfig"
|
source "src/mainboard/thomson/Kconfig"
|
||||||
source "src/mainboard/ti/Kconfig"
|
source "src/mainboard/ti/Kconfig"
|
||||||
source "src/mainboard/traverse/Kconfig"
|
source "src/mainboard/traverse/Kconfig"
|
||||||
|
|
|
||||||
|
|
@ -5,15 +5,12 @@ choice
|
||||||
|
|
||||||
config BOARD_DIGITALLOGIC_ADL855PC
|
config BOARD_DIGITALLOGIC_ADL855PC
|
||||||
bool "smartModule855"
|
bool "smartModule855"
|
||||||
config BOARD_DIGITALLOGIC_MSM586SEG
|
|
||||||
bool "MSM586SEG"
|
|
||||||
config BOARD_DIGITALLOGIC_MSM800SEV
|
config BOARD_DIGITALLOGIC_MSM800SEV
|
||||||
bool "MSM800SEV"
|
bool "MSM800SEV"
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
source "src/mainboard/digitallogic/adl855pc/Kconfig"
|
source "src/mainboard/digitallogic/adl855pc/Kconfig"
|
||||||
source "src/mainboard/digitallogic/msm586seg/Kconfig"
|
|
||||||
source "src/mainboard/digitallogic/msm800sev/Kconfig"
|
source "src/mainboard/digitallogic/msm800sev/Kconfig"
|
||||||
|
|
||||||
config MAINBOARD_VENDOR
|
config MAINBOARD_VENDOR
|
||||||
|
|
|
||||||
|
|
@ -1,23 +0,0 @@
|
||||||
if BOARD_DIGITALLOGIC_MSM586SEG
|
|
||||||
|
|
||||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
|
||||||
def_bool y
|
|
||||||
select CPU_AMD_SC520
|
|
||||||
select HAVE_PIRQ_TABLE
|
|
||||||
select HAVE_OPTION_TABLE
|
|
||||||
select BOARD_ROMSIZE_KB_512
|
|
||||||
select ROMCC
|
|
||||||
|
|
||||||
config MAINBOARD_DIR
|
|
||||||
string
|
|
||||||
default digitallogic/msm586seg
|
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
|
||||||
string
|
|
||||||
default "MSM586SEG"
|
|
||||||
|
|
||||||
config IRQ_SLOT_COUNT
|
|
||||||
int
|
|
||||||
default 2
|
|
||||||
|
|
||||||
endif # BOARD_DIGITALLOGIC_MSM586SEG
|
|
||||||
|
|
@ -1,2 +0,0 @@
|
||||||
Category: half
|
|
||||||
Board URL: http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM586SEG
|
|
||||||
|
|
@ -1,72 +0,0 @@
|
||||||
entries
|
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
|
||||||
#0 8 r 0 seconds
|
|
||||||
#8 8 r 0 alarm_seconds
|
|
||||||
#16 8 r 0 minutes
|
|
||||||
#24 8 r 0 alarm_minutes
|
|
||||||
#32 8 r 0 hours
|
|
||||||
#40 8 r 0 alarm_hours
|
|
||||||
#48 8 r 0 day_of_week
|
|
||||||
#56 8 r 0 day_of_month
|
|
||||||
#64 8 r 0 month
|
|
||||||
#72 8 r 0 year
|
|
||||||
#80 4 r 0 rate_select
|
|
||||||
#84 3 r 0 REF_Clock
|
|
||||||
#87 1 r 0 UIP
|
|
||||||
#88 1 r 0 auto_switch_DST
|
|
||||||
#89 1 r 0 24_hour_mode
|
|
||||||
#90 1 r 0 binary_values_enable
|
|
||||||
#91 1 r 0 square-wave_out_enable
|
|
||||||
#92 1 r 0 update_finished_enable
|
|
||||||
#93 1 r 0 alarm_interrupt_enable
|
|
||||||
#94 1 r 0 periodic_interrupt_enable
|
|
||||||
#95 1 r 0 disable_clock_updates
|
|
||||||
#96 288 r 0 temporary_filler
|
|
||||||
0 384 r 0 reserved_memory
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
385 1 e 4 last_boot
|
|
||||||
386 1 e 1 ECC_memory
|
|
||||||
388 4 r 0 reboot_bits
|
|
||||||
392 3 e 5 baud_rate
|
|
||||||
400 1 e 1 power_on_after_fail
|
|
||||||
412 4 e 6 debug_level
|
|
||||||
416 4 e 7 boot_first
|
|
||||||
420 4 e 7 boot_second
|
|
||||||
424 4 e 7 boot_third
|
|
||||||
428 4 h 0 boot_index
|
|
||||||
432 8 h 0 boot_countdown
|
|
||||||
1008 16 h 0 check_sum
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
5 0 115200
|
|
||||||
5 1 57600
|
|
||||||
5 2 38400
|
|
||||||
5 3 19200
|
|
||||||
5 4 9600
|
|
||||||
5 5 4800
|
|
||||||
5 6 2400
|
|
||||||
5 7 1200
|
|
||||||
6 6 Notice
|
|
||||||
6 7 Info
|
|
||||||
6 8 Debug
|
|
||||||
6 9 Spew
|
|
||||||
7 0 Network
|
|
||||||
7 1 HDD
|
|
||||||
7 2 Floppy
|
|
||||||
7 8 Fallback_Network
|
|
||||||
7 9 Fallback_HDD
|
|
||||||
7 10 Fallback_Floppy
|
|
||||||
#7 3 ROM
|
|
||||||
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 1007 1008
|
|
||||||
|
|
@ -1,7 +0,0 @@
|
||||||
chip cpu/amd/sc520
|
|
||||||
device domain 0 on
|
|
||||||
device pci 0.0 on end
|
|
||||||
device pci 12.0 on end # enet
|
|
||||||
device pci 14.0 on end # 69000
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
@ -1,31 +0,0 @@
|
||||||
/* This file was generated by getpir.c, do not modify!
|
|
||||||
(but if you do, please run checkpir on it to verify)
|
|
||||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
|
||||||
*
|
|
||||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/pirq_routing.h>
|
|
||||||
|
|
||||||
static const struct irq_routing_table intel_irq_routing_table = {
|
|
||||||
PIRQ_SIGNATURE, /* u32 signature */
|
|
||||||
PIRQ_VERSION, /* u16 version */
|
|
||||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
|
||||||
0x00, /* Where the interrupt router lies (bus) */
|
|
||||||
(0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
|
|
||||||
0, /* IRQs devoted exclusively to PCI usage */
|
|
||||||
0x8086, /* Vendor */
|
|
||||||
0x122e, /* Device */
|
|
||||||
0, /* Miniport data */
|
|
||||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
|
||||||
0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
|
||||||
{
|
|
||||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
|
||||||
{0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0},
|
|
||||||
{0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0},
|
|
||||||
}
|
|
||||||
};
|
|
||||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
|
||||||
{
|
|
||||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
|
||||||
}
|
|
||||||
|
|
@ -1,133 +0,0 @@
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include <cpu/amd/sc520.h>
|
|
||||||
|
|
||||||
|
|
||||||
static void irqdump(void)
|
|
||||||
{
|
|
||||||
volatile unsigned char *irq;
|
|
||||||
void *mmcr;
|
|
||||||
int i;
|
|
||||||
int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
|
|
||||||
0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
|
|
||||||
0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
|
|
||||||
0xd30, 0xd31, 0xd32, 0xd33,
|
|
||||||
0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
|
|
||||||
0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
|
|
||||||
-1};
|
|
||||||
mmcr = (void *) 0xfffef000;
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "mmcr is %p\n", mmcr);
|
|
||||||
for(i = 0; irqlist[i] >= 0; i++) {
|
|
||||||
irq = mmcr + irqlist[i];
|
|
||||||
printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/* TODO: finish up mmcr struct in sc520.h, and;
|
|
||||||
- set ADDDECTL (now done in raminit.c in cpu/amd/sc520
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
//volatile struct mmcrpic *pic = MMCRPIC;
|
|
||||||
volatile struct mmcr *mmcr = MMCRDEFAULT;
|
|
||||||
|
|
||||||
/* msm586seg has this register set to a weird value.
|
|
||||||
* follow the board, not the manual!
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* currently, nothing in the device to use, so ignore it. */
|
|
||||||
printk(BIOS_ERR, "digital logic msm586 seg ENTER %s\n", __func__);
|
|
||||||
|
|
||||||
|
|
||||||
/* from fuctory bios */
|
|
||||||
/* NOTE: the following interrupt settings made interrupts work
|
|
||||||
* for hard drive, and serial, but not for ethernet
|
|
||||||
*/
|
|
||||||
/* just do what they say and nobody gets hurt. */
|
|
||||||
mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
|
|
||||||
/* all ints to level */
|
|
||||||
mmcr->pic.mpicmode = 0;
|
|
||||||
mmcr->pic.sl1picmode = 0;
|
|
||||||
mmcr->pic.sl2picmode = 0x80;
|
|
||||||
|
|
||||||
mmcr->pic.intpinpol = 0;
|
|
||||||
|
|
||||||
mmcr->pic.pit0map = 1;
|
|
||||||
mmcr->pic.uart1map = 0xc;
|
|
||||||
mmcr->pic.uart2map = 0xb;
|
|
||||||
mmcr->pic.rtcmap = 3;
|
|
||||||
mmcr->pic.ferrmap = 8;
|
|
||||||
mmcr->pic.gp0imap = 6;
|
|
||||||
mmcr->pic.gp1imap = 2;
|
|
||||||
mmcr->pic.gp2imap = 7;
|
|
||||||
mmcr->pic.gp6imap = 0x15;
|
|
||||||
mmcr->pic.gp7imap = 0x16;
|
|
||||||
mmcr->pic.gp10imap = 0x9;
|
|
||||||
mmcr->pic.gp9imap = 0x4;
|
|
||||||
|
|
||||||
irqdump();
|
|
||||||
printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
|
|
||||||
printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
|
|
||||||
|
|
||||||
/* The following block has NOT proven sufficient to get
|
|
||||||
* the VGA hardware to talk to us
|
|
||||||
*/
|
|
||||||
/* let's set some mmcr stuff per the BIOS settings */
|
|
||||||
mmcr->dbctl.dbctl = 0x10;
|
|
||||||
mmcr->sysarb.ctl = 6;
|
|
||||||
mmcr->sysarb.menb = 0xf;
|
|
||||||
mmcr->sysarb.prictl = 0xc0000f0f;
|
|
||||||
/* this is bios setting, depends on sysarb above */
|
|
||||||
mmcr->hostbridge.ctl = 0x108;
|
|
||||||
printk(BIOS_ERR, "digital logic msm586 seg EXIT %s\n", __func__);
|
|
||||||
|
|
||||||
/* pio */
|
|
||||||
mmcr->pio.data31_16 = 0xffbf;
|
|
||||||
|
|
||||||
/* pci stuff */
|
|
||||||
mmcr->pic.pciintamap = 0xa;
|
|
||||||
|
|
||||||
/* END block where vga hardware still will not talk to us */
|
|
||||||
/* all we get from VGA I/O addresses are ffff etc.
|
|
||||||
*/
|
|
||||||
mmcr->sysmap.adddecctl = 0x10;
|
|
||||||
|
|
||||||
/* VGA now talks to us, so this adddecctl was the trick.
|
|
||||||
* still no interrupts from enet.
|
|
||||||
* Let's try fixing the piodata stuff, as there may be
|
|
||||||
* some wire there not documented.
|
|
||||||
*/
|
|
||||||
mmcr->pio.data31_16 = 0xffbf;
|
|
||||||
/* also, our sl?picmode needs to match fuctory bios */
|
|
||||||
mmcr->pic.sl1picmode = 0x80;
|
|
||||||
mmcr->pic.sl2picmode = 0x0;
|
|
||||||
/* and, finally, they do set gp5imap and we don't.
|
|
||||||
*/
|
|
||||||
mmcr->pic.gp5imap = 0xd;
|
|
||||||
/* remaining problem: almost certainly, the irq table is bogus
|
|
||||||
* NO SHOCK as it came from fuctory bios.
|
|
||||||
* but let's try these 4 changes for now and see what shakes.
|
|
||||||
*/
|
|
||||||
/* still not interrupts. */
|
|
||||||
/* their IRQ table is wrong. Just hardwire it */
|
|
||||||
{
|
|
||||||
unsigned char pciints[4] = {15, 15, 15, 15};
|
|
||||||
pci_assign_irqs(0, 12, pciints);
|
|
||||||
}
|
|
||||||
/* the assigned failed but we just noticed -- there is no
|
|
||||||
* dma mapping, and selftest on e100 requires that dma work
|
|
||||||
*/
|
|
||||||
/* follow fuctory here */
|
|
||||||
mmcr->dmacontrol.extchanmapa = 0x3210;
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
};
|
|
||||||
|
|
@ -1,239 +0,0 @@
|
||||||
#include <stdint.h>
|
|
||||||
#include <device/pci_def.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include <device/pnp_def.h>
|
|
||||||
#include <pc80/mc146818rtc.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include "cpu/x86/bist.h"
|
|
||||||
|
|
||||||
void setup_pars(void)
|
|
||||||
{
|
|
||||||
volatile unsigned long *par;
|
|
||||||
/* as per the book: */
|
|
||||||
/* PAR register setup */
|
|
||||||
/* set up the PAR registers as they are on the MSM586SEG */
|
|
||||||
par = (unsigned long *) 0xfffef088;
|
|
||||||
|
|
||||||
/* NOTE: move this to mainboard.c ASAP */
|
|
||||||
*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
|
|
||||||
*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
|
|
||||||
*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
|
|
||||||
*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
|
|
||||||
*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
|
|
||||||
*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
|
|
||||||
*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
|
|
||||||
*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
|
|
||||||
*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
|
|
||||||
*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
|
|
||||||
*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
|
|
||||||
*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
|
|
||||||
*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
|
|
||||||
*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
|
|
||||||
*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
|
|
||||||
*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
|
|
||||||
}
|
|
||||||
|
|
||||||
#include "cpu/amd/sc520/raminit.c"
|
|
||||||
|
|
||||||
struct mem_controller {
|
|
||||||
int i;
|
|
||||||
};
|
|
||||||
|
|
||||||
static int spd_read_byte(unsigned device, unsigned address) { }
|
|
||||||
|
|
||||||
static inline void dumpmem(void){
|
|
||||||
int i, j;
|
|
||||||
unsigned char *l;
|
|
||||||
unsigned char c;
|
|
||||||
|
|
||||||
for(i = 0x4000; i < 0x5000; i += 16) {
|
|
||||||
print_err_hex32(i); print_err(":");
|
|
||||||
for(j = 0; j < 16; j++) {
|
|
||||||
l = (unsigned char *)i + j;
|
|
||||||
c = *l;
|
|
||||||
print_err_hex8(c);
|
|
||||||
print_err(" ");
|
|
||||||
}
|
|
||||||
print_err("\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void irqinit(void){
|
|
||||||
volatile unsigned char *cp;
|
|
||||||
#if 0
|
|
||||||
/* these values taken from the msm board itself.
|
|
||||||
* and they cause the board to not even come out of calibrating_delay_loop
|
|
||||||
* if you can believe it. Our problem right now is no IDE or serial interrupts
|
|
||||||
* So we'll try to put interrupts in, one at a time. IDE first.
|
|
||||||
*/
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd00;
|
|
||||||
*cp = 0x11;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd02;
|
|
||||||
*cp = 0x02;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd03;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd04;
|
|
||||||
*cp = 0xf7;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd08;
|
|
||||||
*cp = 0xf7;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd0a;
|
|
||||||
*cp = 0x8b;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd10;
|
|
||||||
*cp = 0x18;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd14;
|
|
||||||
*cp = 0x09;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd18;
|
|
||||||
*cp = 0x88;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd1a;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd1b;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd1c;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd20;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd21;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd22;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd28;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd29;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd30;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd31;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd32;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd33;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd40;
|
|
||||||
*cp = 0x10;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd41;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd42;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd43;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd44;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd45;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd46;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd50;
|
|
||||||
*cp = 0x37;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd51;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd52;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd53;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd54;
|
|
||||||
*cp = 0x37;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd55;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd56;
|
|
||||||
*cp = 0x37;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd57;
|
|
||||||
*cp = 0x00;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd58;
|
|
||||||
*cp = 0xff;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd59;
|
|
||||||
*cp = 0xff;
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd5a;
|
|
||||||
*cp = 0xff;
|
|
||||||
#endif
|
|
||||||
#if 0
|
|
||||||
/* this fails too */
|
|
||||||
/* IDE only ... */
|
|
||||||
cp = (volatile unsigned char *) 0xfffefd56;
|
|
||||||
*cp = 0xe;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#include <cpu/intel/romstage.h>
|
|
||||||
static void main(unsigned long bist)
|
|
||||||
{
|
|
||||||
volatile int i;
|
|
||||||
for(i = 0; i < 100; i++)
|
|
||||||
;
|
|
||||||
|
|
||||||
setupsc520();
|
|
||||||
irqinit();
|
|
||||||
console_init();
|
|
||||||
for(i = 0; i < 100; i++)
|
|
||||||
print_err("fill usart\n");
|
|
||||||
// while(1)
|
|
||||||
print_err("HI THERE!\n");
|
|
||||||
// sizemem();
|
|
||||||
staticmem();
|
|
||||||
|
|
||||||
/* Void warranty when label is removed. */
|
|
||||||
dummy_romcc_workaround_label:
|
|
||||||
do { } while (0);
|
|
||||||
|
|
||||||
print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60);
|
|
||||||
print_err("\n");
|
|
||||||
|
|
||||||
// while(1)
|
|
||||||
print_err("STATIC MEM DONE\n");
|
|
||||||
post_code(0xee);
|
|
||||||
print_err("loop forever ...\n");
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
|
|
||||||
/* clear memory 1meg */
|
|
||||||
__asm__ volatile(
|
|
||||||
"1: \n\t"
|
|
||||||
"movl %0, %%fs:(%1)\n\t"
|
|
||||||
"addl $4,%1\n\t"
|
|
||||||
"subl $4,%2\n\t"
|
|
||||||
"jnz 1b\n\t"
|
|
||||||
:
|
|
||||||
: "a" (0), "D" (0), "c" (1024*1024)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
dump_pci_devices();
|
|
||||||
#endif
|
|
||||||
#if 0
|
|
||||||
dump_pci_device(PCI_DEV(0, 0, 0));
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if 1
|
|
||||||
{
|
|
||||||
volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000;
|
|
||||||
volatile unsigned char *dst = (unsigned char *) 0x4000;
|
|
||||||
for(i = 0; i < 0x20000; i++) {
|
|
||||||
/*
|
|
||||||
print_err("Set dst "); print_err_hex32((unsigned long) dst);
|
|
||||||
print_err(" to "); print_err_hex32(*src); print_err("\n");
|
|
||||||
*/
|
|
||||||
*dst = *src;
|
|
||||||
//print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
|
|
||||||
dst++, src++;
|
|
||||||
post_code(i & 0xff);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
dumpmem();
|
|
||||||
post_code(0x00);
|
|
||||||
|
|
||||||
print_err("loop forever\n");
|
|
||||||
post_code(0xdd);
|
|
||||||
__asm__ volatile(
|
|
||||||
"movl %0, %%edi\n\t"
|
|
||||||
"jmp *%%edi\n\t"
|
|
||||||
:
|
|
||||||
: "a" (0x4000)
|
|
||||||
);
|
|
||||||
|
|
||||||
print_err("Oh dear, I'm afraid it didn't work...\n");
|
|
||||||
|
|
||||||
while(1);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
@ -1,17 +0,0 @@
|
||||||
if VENDOR_TECHNOLOGIC
|
|
||||||
|
|
||||||
choice
|
|
||||||
prompt "Mainboard model"
|
|
||||||
|
|
||||||
config BOARD_TECHNOLOGIC_TS5300
|
|
||||||
bool "TS-5300"
|
|
||||||
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
source "src/mainboard/technologic/ts5300/Kconfig"
|
|
||||||
|
|
||||||
config MAINBOARD_VENDOR
|
|
||||||
string
|
|
||||||
default "Technologic"
|
|
||||||
|
|
||||||
endif # VENDOR_TECHNOLOGIC
|
|
||||||
|
|
@ -1,23 +0,0 @@
|
||||||
if BOARD_TECHNOLOGIC_TS5300
|
|
||||||
|
|
||||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
|
||||||
def_bool y
|
|
||||||
select CPU_AMD_SC520
|
|
||||||
select ROMCC
|
|
||||||
select HAVE_OPTION_TABLE
|
|
||||||
select HAVE_PIRQ_TABLE
|
|
||||||
select BOARD_ROMSIZE_KB_1024
|
|
||||||
|
|
||||||
config MAINBOARD_DIR
|
|
||||||
string
|
|
||||||
default technologic/ts5300
|
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
|
||||||
string
|
|
||||||
default "TS-5300"
|
|
||||||
|
|
||||||
config IRQ_SLOT_COUNT
|
|
||||||
int
|
|
||||||
default 2
|
|
||||||
|
|
||||||
endif # BOARD_TECHNOLOGIC_TS5300
|
|
||||||
|
|
@ -1,2 +0,0 @@
|
||||||
Category: half
|
|
||||||
Board URL: http://www.embeddedarm.com/epc/ts5300-spec-h.html
|
|
||||||
|
|
@ -1,72 +0,0 @@
|
||||||
entries
|
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
|
||||||
#0 8 r 0 seconds
|
|
||||||
#8 8 r 0 alarm_seconds
|
|
||||||
#16 8 r 0 minutes
|
|
||||||
#24 8 r 0 alarm_minutes
|
|
||||||
#32 8 r 0 hours
|
|
||||||
#40 8 r 0 alarm_hours
|
|
||||||
#48 8 r 0 day_of_week
|
|
||||||
#56 8 r 0 day_of_month
|
|
||||||
#64 8 r 0 month
|
|
||||||
#72 8 r 0 year
|
|
||||||
#80 4 r 0 rate_select
|
|
||||||
#84 3 r 0 REF_Clock
|
|
||||||
#87 1 r 0 UIP
|
|
||||||
#88 1 r 0 auto_switch_DST
|
|
||||||
#89 1 r 0 24_hour_mode
|
|
||||||
#90 1 r 0 binary_values_enable
|
|
||||||
#91 1 r 0 square-wave_out_enable
|
|
||||||
#92 1 r 0 update_finished_enable
|
|
||||||
#93 1 r 0 alarm_interrupt_enable
|
|
||||||
#94 1 r 0 periodic_interrupt_enable
|
|
||||||
#95 1 r 0 disable_clock_updates
|
|
||||||
#96 288 r 0 temporary_filler
|
|
||||||
0 384 r 0 reserved_memory
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
385 1 e 4 last_boot
|
|
||||||
386 1 e 1 ECC_memory
|
|
||||||
388 4 r 0 reboot_bits
|
|
||||||
392 3 e 5 baud_rate
|
|
||||||
400 1 e 1 power_on_after_fail
|
|
||||||
412 4 e 6 debug_level
|
|
||||||
416 4 e 7 boot_first
|
|
||||||
420 4 e 7 boot_second
|
|
||||||
424 4 e 7 boot_third
|
|
||||||
428 4 h 0 boot_index
|
|
||||||
432 8 h 0 boot_countdown
|
|
||||||
1008 16 h 0 check_sum
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
5 0 115200
|
|
||||||
5 1 57600
|
|
||||||
5 2 38400
|
|
||||||
5 3 19200
|
|
||||||
5 4 9600
|
|
||||||
5 5 4800
|
|
||||||
5 6 2400
|
|
||||||
5 7 1200
|
|
||||||
6 6 Notice
|
|
||||||
6 7 Info
|
|
||||||
6 8 Debug
|
|
||||||
6 9 Spew
|
|
||||||
7 0 Network
|
|
||||||
7 1 HDD
|
|
||||||
7 2 Floppy
|
|
||||||
7 8 Fallback_Network
|
|
||||||
7 9 Fallback_HDD
|
|
||||||
7 10 Fallback_Floppy
|
|
||||||
#7 3 ROM
|
|
||||||
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 1007 1008
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
chip cpu/amd/sc520
|
|
||||||
device domain 0 on
|
|
||||||
device pci 0.0 on end
|
|
||||||
end
|
|
||||||
|
|
||||||
end
|
|
||||||
|
|
@ -1,31 +0,0 @@
|
||||||
/* This file was generated by getpir.c, do not modify!
|
|
||||||
(but if you do, please run checkpir on it to verify)
|
|
||||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
|
||||||
*
|
|
||||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/pirq_routing.h>
|
|
||||||
|
|
||||||
static const struct irq_routing_table intel_irq_routing_table = {
|
|
||||||
PIRQ_SIGNATURE, /* u32 signature */
|
|
||||||
PIRQ_VERSION, /* u16 version */
|
|
||||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
|
||||||
0x00, /* Where the interrupt router lies (bus) */
|
|
||||||
(0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
|
|
||||||
0, /* IRQs devoted exclusively to PCI usage */
|
|
||||||
0x8086, /* Vendor */
|
|
||||||
0x122e, /* Device */
|
|
||||||
0, /* Miniport data */
|
|
||||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
|
||||||
0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
|
||||||
{
|
|
||||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
|
||||||
{0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0},
|
|
||||||
{0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0},
|
|
||||||
}
|
|
||||||
};
|
|
||||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
|
||||||
{
|
|
||||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
|
||||||
}
|
|
||||||
|
|
@ -1,147 +0,0 @@
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include <cpu/amd/sc520.h>
|
|
||||||
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
static void irqdump(void)
|
|
||||||
{
|
|
||||||
volatile unsigned char *irq;
|
|
||||||
void *mmcr;
|
|
||||||
|
|
||||||
|
|
||||||
int i;
|
|
||||||
int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
|
|
||||||
0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
|
|
||||||
0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
|
|
||||||
0xd30, 0xd31, 0xd32, 0xd33,
|
|
||||||
0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
|
|
||||||
0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
|
|
||||||
-1};
|
|
||||||
mmcr = (void *) 0xfffef000;
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "mmcr is %p\n", mmcr);
|
|
||||||
for(i = 0; irqlist[i] >= 0; i++) {
|
|
||||||
irq = mmcr + irqlist[i];
|
|
||||||
printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* TODO: finish up mmcr struct in sc520.h, and;
|
|
||||||
- set ADDDECTL (now done in raminit.c in cpu/amd/sc520
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
volatile struct mmcr *mmcr = MMCRDEFAULT;
|
|
||||||
|
|
||||||
/* currently, nothing in the device to use, so ignore it. */
|
|
||||||
printk(BIOS_ERR, "Technologic Systems 5300 ENTER %s\n", __func__);
|
|
||||||
|
|
||||||
/* from fuctory bios */
|
|
||||||
/* NOTE: the following interrupt settings made interrupts work
|
|
||||||
* for hard drive, and serial, but not for ethernet
|
|
||||||
*/
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "Setting up PIC\n");
|
|
||||||
/* just do what they say and nobody gets hurt. */
|
|
||||||
mmcr->pic.pcicr = 0 ;
|
|
||||||
/* all ints to level */
|
|
||||||
mmcr->pic.mpicmode = 0;
|
|
||||||
mmcr->pic.sl1picmode = 0;
|
|
||||||
mmcr->pic.sl2picmode = 0;
|
|
||||||
|
|
||||||
mmcr->pic.intpinpol = 0x100;
|
|
||||||
|
|
||||||
mmcr->pic.pit0map = 1;
|
|
||||||
mmcr->pic.uart1map = 0x0c;
|
|
||||||
mmcr->pic.uart2map = 0x0b;
|
|
||||||
mmcr->pic.rtcmap = 0x03;
|
|
||||||
mmcr->pic.ferrmap = 0x00;
|
|
||||||
mmcr->pic.intpinpol = 0x100;
|
|
||||||
|
|
||||||
mmcr->pic.gp0imap = 0x00;
|
|
||||||
mmcr->pic.gp1imap = 0x02;
|
|
||||||
mmcr->pic.gp2imap = 0x07;
|
|
||||||
mmcr->pic.gp3imap = 0x05;
|
|
||||||
mmcr->pic.gp4imap = 0x06;
|
|
||||||
mmcr->pic.gp5imap = 0x0d;
|
|
||||||
mmcr->pic.gp6imap = 0x15;
|
|
||||||
mmcr->pic.gp7imap = 0x16;
|
|
||||||
mmcr->pic.gp8imap = 0x3;
|
|
||||||
mmcr->pic.gp9imap = 0x4;
|
|
||||||
mmcr->pic.gp10imap = 0x9;
|
|
||||||
|
|
||||||
// irqdump();
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "Setting up sysarb\n");
|
|
||||||
mmcr->dbctl.dbctl = 0x01;
|
|
||||||
mmcr->sysarb.ctl = 0x00;
|
|
||||||
mmcr->sysarb.menb = 0x1f;
|
|
||||||
mmcr->sysarb.prictl = 0x40000f0f;
|
|
||||||
|
|
||||||
/* this is bios setting, depends on sysarb above */
|
|
||||||
mmcr->hostbridge.ctl = 0x0;
|
|
||||||
mmcr->hostbridge.tgtirqctl = 0x0;
|
|
||||||
mmcr->hostbridge.tgtirqsta = 0xf00;
|
|
||||||
mmcr->hostbridge.mstirqctl = 0x0;
|
|
||||||
mmcr->hostbridge.mstirqsta = 0x708;
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "Setting up pio\n");
|
|
||||||
/* pio */
|
|
||||||
mmcr->pio.pfs15_0 = 0xffff;
|
|
||||||
mmcr->pio.pfs31_16 = 0xffff;
|
|
||||||
mmcr->pio.cspfs = 0xfe;
|
|
||||||
mmcr->pio.clksel = 0x13;
|
|
||||||
mmcr->pio.dsctl = 0x200;
|
|
||||||
mmcr->pio.data15_0 = 0xde04;
|
|
||||||
mmcr->pio.data31_16 = 0xef9f;
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "Setting up sysmap\n");
|
|
||||||
/* system memory map */
|
|
||||||
mmcr->sysmap.adddecctl = 0x04;
|
|
||||||
mmcr->sysmap.wpvsta = 0x8006;
|
|
||||||
mmcr->sysmap.par[1] = 0x340f0070;
|
|
||||||
mmcr->sysmap.par[2] = 0x380701f0;
|
|
||||||
mmcr->sysmap.par[3] = 0x3c0103f6;
|
|
||||||
mmcr->sysmap.par[4] = 0x2c0f0300;
|
|
||||||
mmcr->sysmap.par[5] = 0x447c00a0;
|
|
||||||
mmcr->sysmap.par[6] = 0xe600000c;
|
|
||||||
mmcr->sysmap.par[7] = 0x300046e8;
|
|
||||||
mmcr->sysmap.par[8] = 0x500400d0;
|
|
||||||
mmcr->sysmap.par[9] = 0x281f0140;
|
|
||||||
mmcr->sysmap.par[13] = 0x8a07c940;
|
|
||||||
mmcr->sysmap.par[15] = 0xee00400e;
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "Setting up gpctl\n");
|
|
||||||
mmcr->gpctl.gpcsrt = 0x01;
|
|
||||||
mmcr->gpctl.gpcspw = 0x09;
|
|
||||||
mmcr->gpctl.gpcsoff = 0x01;
|
|
||||||
mmcr->gpctl.gprdw = 0x07;
|
|
||||||
mmcr->gpctl.gprdoff = 0x02;
|
|
||||||
mmcr->gpctl.gpwrw = 0x07;
|
|
||||||
mmcr->gpctl.gpwroff = 0x02;
|
|
||||||
|
|
||||||
//mmcr->reset.sysinfo = 0xdf;
|
|
||||||
//mmcr->reset.rescfg = 0x5;
|
|
||||||
/* their IRQ table is wrong. Just hardwire it */
|
|
||||||
//{
|
|
||||||
// char pciints[4] = {15, 15, 15, 15};
|
|
||||||
// pci_assign_irqs(0, 12, pciints);
|
|
||||||
//}
|
|
||||||
/* the assigned failed but we just noticed -- there is no
|
|
||||||
* dma mapping, and selftest on e100 requires that dma work
|
|
||||||
*/
|
|
||||||
mmcr->dmacontrol.extchanmapa = 0xf210;
|
|
||||||
mmcr->dmacontrol.extchanmapb = 0xffff;
|
|
||||||
|
|
||||||
printk(BIOS_ERR, "TS5300 EXIT %s\n", __func__);
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
};
|
|
||||||
|
|
@ -1,168 +0,0 @@
|
||||||
/*
|
|
||||||
* TS5300 specific initialization code.
|
|
||||||
* written by Stefan Reinauer <stepan@coresystems.de>
|
|
||||||
* (c) 2006 coresystems GmbH
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <device/pci_def.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include <device/pnp_def.h>
|
|
||||||
#include <pc80/mc146818rtc.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include "cpu/x86/bist.h"
|
|
||||||
|
|
||||||
#define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77)
|
|
||||||
#define TS5300_LED_ON outb((inb(0x77)|1), 0x77)
|
|
||||||
|
|
||||||
#define TS9500_LED_OFF outb((inb(0x19a)&0xfe), 0x19a)
|
|
||||||
#define TS9500_LED_ON outb((inb(0x19a)|1), 0x19a)
|
|
||||||
|
|
||||||
/* PAR register setup */
|
|
||||||
void setup_pars(void)
|
|
||||||
{
|
|
||||||
volatile unsigned long *par;
|
|
||||||
par = (unsigned long *) 0xfffef088;
|
|
||||||
|
|
||||||
/* NOTE: Ron says, move this to mainboard.c */
|
|
||||||
*par++ = 0x00000000;
|
|
||||||
*par++ = 0x340f0070;
|
|
||||||
*par++ = 0x380701f0;
|
|
||||||
*par++ = 0x3c0103f6;
|
|
||||||
*par++ = 0x2c0f0300;
|
|
||||||
*par++ = 0x447c00a0;
|
|
||||||
*par++ = 0xe600000c;
|
|
||||||
*par++ = 0x300046e8;
|
|
||||||
*par++ = 0x500400d0;
|
|
||||||
*par++ = 0x281f0140;
|
|
||||||
*par++ = 0x00000000;
|
|
||||||
*par++ = 0x00000000;
|
|
||||||
*par++ = 0x00000000;
|
|
||||||
*par++ = 0x8a07c940; /* Flash setup */
|
|
||||||
*par++ = 0x00000000;
|
|
||||||
*par++ = 0xee00400e;
|
|
||||||
}
|
|
||||||
|
|
||||||
#include "cpu/amd/sc520/raminit.c"
|
|
||||||
|
|
||||||
static void identify_ts9500(void)
|
|
||||||
{
|
|
||||||
unsigned i, val;
|
|
||||||
|
|
||||||
TS9500_LED_ON;
|
|
||||||
|
|
||||||
print_err("TS-9500 add-on found:\n");
|
|
||||||
val=inb(0x19b);
|
|
||||||
for (i=0; i<8; i++) {
|
|
||||||
print_err(" DIP");
|
|
||||||
print_err_char(i+0x31);
|
|
||||||
print_err(": ");
|
|
||||||
if((val&(1<<i))!=0)
|
|
||||||
print_err("on\n");
|
|
||||||
else
|
|
||||||
print_err("off\n");
|
|
||||||
}
|
|
||||||
print_err("\n");
|
|
||||||
|
|
||||||
val=inb(0x19a);
|
|
||||||
|
|
||||||
for (i=6; i<8; i++) {
|
|
||||||
print_err(" JP");
|
|
||||||
print_err_char(i+0x30-5);
|
|
||||||
print_err(": ");
|
|
||||||
if((val&(1<<i))!=0)
|
|
||||||
print_err("on\n");
|
|
||||||
else
|
|
||||||
print_err("off\n");
|
|
||||||
}
|
|
||||||
print_err("\n");
|
|
||||||
|
|
||||||
TS9500_LED_OFF;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void identify_system(void)
|
|
||||||
{
|
|
||||||
unsigned i,val;
|
|
||||||
|
|
||||||
print_err("Mainboard: ");
|
|
||||||
val=inb(0x74);
|
|
||||||
switch(val) {
|
|
||||||
case 0x50: print_err("TS-5300\n"); break;
|
|
||||||
case 0x40: print_err("TS-5400\n"); break;
|
|
||||||
case 0x60: print_err("TS-5500\n"); break;
|
|
||||||
case 0x20: print_err("TS-5600\n"); break;
|
|
||||||
case 0x70: print_err("TS-5700\n"); break;
|
|
||||||
default: print_err("unknown\n"); break;
|
|
||||||
}
|
|
||||||
|
|
||||||
val=inb(0x75);
|
|
||||||
print_err(" SRAM option: ");
|
|
||||||
if((val&1)==0) print_err("not ");
|
|
||||||
print_err("installed\n");
|
|
||||||
|
|
||||||
print_err(" RS-485 option: ");
|
|
||||||
if((val&2)==0) print_err("not ");
|
|
||||||
print_err("installed\n");
|
|
||||||
|
|
||||||
val=inb(0x76);
|
|
||||||
print_err(" Temp. range: ");
|
|
||||||
if((val&2)==0) print_err("commercial\n");
|
|
||||||
else print_err("industrial\n");
|
|
||||||
|
|
||||||
print_err("\n");
|
|
||||||
|
|
||||||
val=inb(0x77);
|
|
||||||
for (i=1; i<8; i++) {
|
|
||||||
print_err(" JP");
|
|
||||||
print_err_char(i+0x30);
|
|
||||||
print_err(": ");
|
|
||||||
if((val&(1<<i))!=0)
|
|
||||||
print_err("on\n");
|
|
||||||
else
|
|
||||||
print_err("off\n");
|
|
||||||
}
|
|
||||||
print_err("\n");
|
|
||||||
|
|
||||||
/* Detect TS-9500 */
|
|
||||||
val=inb(0x19d);
|
|
||||||
if(val==0x5f)
|
|
||||||
identify_ts9500();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void hard_reset(void)
|
|
||||||
{
|
|
||||||
print_err("Hard reset called.\n");
|
|
||||||
while (1) ;
|
|
||||||
}
|
|
||||||
|
|
||||||
#include <cpu/intel/romstage.h>
|
|
||||||
static void main(unsigned long bist)
|
|
||||||
{
|
|
||||||
volatile int i;
|
|
||||||
unsigned val;
|
|
||||||
|
|
||||||
TS5300_LED_ON;
|
|
||||||
|
|
||||||
// Let the hardware settle a bit.
|
|
||||||
for(i = 0; i < 100; i++)
|
|
||||||
;
|
|
||||||
|
|
||||||
setupsc520();
|
|
||||||
console_init();
|
|
||||||
|
|
||||||
|
|
||||||
print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n");
|
|
||||||
staticmem();
|
|
||||||
|
|
||||||
/* Void warranty when label is removed. */
|
|
||||||
dummy_romcc_workaround_label:
|
|
||||||
do { } while (0);
|
|
||||||
|
|
||||||
print_err("Memory initialized: 32MB\n");
|
|
||||||
|
|
||||||
#if 1
|
|
||||||
identify_system();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
TS5300_LED_OFF;
|
|
||||||
}
|
|
||||||
Loading…
Reference in New Issue