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mb/supermicro/x10slm-f: Do SIO setup in bootblock 

Lynx Point switched to doing mainboard-specific super I/O setup in the
bootblock with commit d893a2635f ("sb/intel/lynxpoint: Enable LPC/SIO
setup in bootblock"). The X10SLM+-F was added while that commit was in
review, and hence did not receive the necessary changes to SIO setup.

This patch has not been tested on hardware.

Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Tristan Corrick 2019-04-24 01:24:30 +12:00 committed by Patrick Georgi
parent 5849b14705
commit 478a1212ef
3 changed files with 42 additions and 24 deletions
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1
src/mainboard/supermicro/x10slm-f/Makefile.inc
View File

@ -15,3 +15,4 @@
## ##
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += bootblock.c

41
src/mainboard/supermicro/x10slm-f/bootblock.c Normal file
View File

@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pnp_ops.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_superio(void)
{
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
/* Select HWM/LED functions instead of floppy functions. */
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
/* Power RAM in S3 and let the PCH handle power failure actions. */
pnp_set_logical_device(ACPI_DEV);
pnp_write_config(ACPI_DEV, 0xe4, 0x70);
nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
}

24
src/mainboard/supermicro/x10slm-f/romstage.c
View File

@ -17,14 +17,11 @@
#include <cpu/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h> #include <northbridge/intel/haswell/pei_data.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
#include <stdint.h> #include <stdint.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
static const struct rcba_config_instruction rcba_config[] = { static const struct rcba_config_instruction rcba_config[] = {
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
@ -41,27 +38,6 @@ static const struct rcba_config_instruction rcba_config[] = {
RCBA_END_CONFIG, RCBA_END_CONFIG,
}; };
void mainboard_config_superio(void)
{
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
/* Select HWM/LED functions instead of floppy functions. */
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
/* Power RAM in S3 and let the PCH handle power failure actions. */
pnp_set_logical_device(ACPI_DEV);
pnp_write_config(ACPI_DEV, 0xe4, 0x70);
nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
}
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(unsigned long bist)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {