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nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree 

Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid
probing by the MRC. We can do that for all boards instead, based on the
devicetree setting.

Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2019-11-17 02:58:00 +01:00 committed by Patrick Georgi
parent 6760e0bdcd
commit 47bf498681
7 changed files with 13 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/butterfly/early_init.c
View File

@ -30,8 +30,6 @@
void mainboard_late_rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P1IP WLAN INTA -> PIRQB
@ -68,12 +66,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {

8
src/mainboard/google/parrot/early_init.c
View File

@ -28,8 +28,6 @@
void mainboard_late_rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P2IP WLAN INTA -> PIRQB
@ -67,12 +65,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
void mainboard_fill_pei_data(struct pei_data *pei_data)

8
src/mainboard/google/stout/early_init.c
View File

@ -32,8 +32,6 @@
void mainboard_late_rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D20IP_XHCI XHCI INTA -> PIRQD (MSI)
@ -71,12 +69,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
/*

3
src/mainboard/intel/dcp847ske/early_southbridge.c
View File

@ -30,9 +30,6 @@
void mainboard_late_rcba_config(void)
{
/* Disable devices */
RCBA32(FD) |= PCH_DISABLE_P2P;
/* Set "mobile" bit in MCH (which makes sense layout-wise). */
/* Note sure if this has any effect at all though. */
MCHBAR32(0x0004) |= 0x00001000;

11
src/mainboard/kontron/ktqm77/early_init.c
View File

@ -44,17 +44,6 @@ void mainboard_pch_lpc_setup(void)
COMA_LPC_EN | COMB_LPC_EN);
}
void mainboard_late_rcba_config(void)
{
u32 reg32;
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
void bootblock_mainboard_early_init(void)
{
int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */

11
src/mainboard/roda/rv11/early_init.c
View File

@ -16,17 +16,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_late_rcba_config(void)
{
u32 reg32;
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
int mainboard_should_reset_usb(int s3resume)
{
return !s3resume;

13
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -18,6 +18,7 @@
#include <bootmode.h>
#include <cf9_reset.h>
#include <string.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cbmem.h>
@ -382,6 +383,16 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data)
pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams;
}
static void disable_p2p(void)
{
/* Disable PCI-to-PCI bridge early to prevent probing by MRC. */
const struct device *const p2p = pcidev_on_root(0x1e, 0);
if (p2p && p2p->enabled)
return;
RCBA32(FD) |= PCH_DISABLE_P2P;
}
void perform_raminit(int s3resume)
{
int cbmem_was_initted;
@ -423,6 +434,8 @@ void perform_raminit(int s3resume)
}
}
disable_p2p();
pei_data.boot_mode = s3resume ? 2 : 0;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);