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mb/google/rex: Set `SkipExtGfxScan` FSP-M UPD 

This patch overrides `SkipExtGfxScan` UPD as the Rex device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.

BUG=b:228002764
TEST=Able to save ~1ms+ boot time on google/rex.

FSP FPDT Data is showing the timestamp between those function calls.

Without this patch:
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131

With this patch:

`CheckOffboardPcieVga` is not getting called.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2023-02-10 21:10:06 +05:30 committed by Eric Lai
parent f57eb1a640
commit 487cd399df
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
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@ -20,6 +20,9 @@ chip soc/intel/meteorlake
# Enable CNVi BT
register "cnvi_bt_core" = "true"
# Set on-board graphics as primary display
register "skip_ext_gfx_scan" = "1"
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,