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Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an 

example.

This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>                                                                                                                                          



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2011-04-26 23:47:04 +00:00 committed by Stefan Reinauer
parent 3187d0267d
commit 4885daadb3
20 changed files with 478 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/Kconfig
View File

@ -159,6 +159,15 @@ config MMCONF_SUPPORT
source src/console/Kconfig
# This should default to N and be set by SuperI/O drivers that have an UART
config HAVE_UART_IO_MAPPED
bool
default y
config HAVE_UART_MEMORY_MAPPED
bool
default n
config HAVE_ACPI_RESUME
bool
default n

3
src/arch/x86/boot/coreboot_table.c
View File

@ -135,6 +135,9 @@ static void lb_console(struct lb_header *header)
#if CONFIG_CONSOLE_SERIAL8250
add_console(header, LB_TAG_CONSOLE_SERIAL8250);
#endif
#if CONFIG_CONSOLE_SERIAL8250MEM
add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM);
#endif
#if CONFIG_CONSOLE_LOGBUF
add_console(header, LB_TAG_CONSOLE_LOGBUF);
#endif

5
src/arch/x86/lib/romstage_console.c
View File

@ -19,7 +19,7 @@
#include <console/console.h>
#include <console/vtxprintf.h>
#if CONFIG_CONSOLE_SERIAL8250
#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
#include <uart8250.h>
#endif
#if CONFIG_USBDEBUG
@ -34,6 +34,9 @@ static void console_tx_byte(unsigned char byte)
if (byte == '\n')
console_tx_byte('\r');
#if CONFIG_CONSOLE_SERIAL8250MEM
uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
#endif
#if CONFIG_CONSOLE_SERIAL8250
uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
#endif

13
src/console/Kconfig
View File

@ -2,9 +2,16 @@ menu "Console"
# TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete.
config CONSOLE_SERIAL8250
bool "Serial port console output"
depends on HAVE_UART_IO_MAPPED
default y
help
Send coreboot debug output to a serial port console.
Send coreboot debug output to an I/O mapped serial port console.
config CONSOLE_SERIAL8250MEM
bool "Serial port console output (memory mapped)"
depends on HAVE_UART_MEMORY_MAPPED
help
Send coreboot debug output to a memory mapped serial port console.
choice
prompt "Serial port"
@ -43,7 +50,7 @@ config TTYS0_BASE
choice
prompt "Baud rate"
default CONSOLE_SERIAL_115200
depends on CONSOLE_SERIAL8250
depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
config CONSOLE_SERIAL_115200
bool "115200"
@ -82,7 +89,7 @@ config TTYS0_BAUD
config TTYS0_LCS
int
default 3
depends on CONSOLE_SERIAL8250
depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
config HAVE_USBDEBUG

1
src/console/Makefile.inc
View File

@ -14,6 +14,7 @@ romstage-y += post.c
romstage-y += die.c
driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c
driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c
driver-$(CONFIG_USBDEBUG) += usbdebug_console.c
driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c
driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c

5
src/console/console.c
View File

@ -22,7 +22,7 @@
#include <arch/hlt.h>
#include <arch/io.h>
#if CONFIG_CONSOLE_SERIAL8250
#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
#include <uart8250.h>
#endif
@ -106,6 +106,9 @@ void console_init(void)
#if CONFIG_CONSOLE_SERIAL8250
uart_init();
#endif
#if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM
oxford_init();
#endif
#if CONFIG_CONSOLE_NE2K
ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
#endif

60
src/console/uart8250mem_console.c Normal file
View File

@ -0,0 +1,60 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <uart8250.h>
#include <pc80/mc146818rtc.h>
static u32 uart_bar = 0;
static void uartmem_init(void)
{
uart_bar = uart_mem_init();
}
static void uartmem_tx_byte(unsigned char data)
{
if (!uart_bar)
return;
uart8250_mem_tx_byte(uart_bar, data);
}
static unsigned char uartmem_rx_byte(void)
{
if (!uart_bar)
return 0;
return uart8250_mem_rx_byte(uart_bar);
}
static int uartmem_tst_byte(void)
{
if (!uart_bar)
return 0;
return uart8250_mem_can_rx_byte(uart_bar);
}
static const struct console_driver uart8250mem_console __console = {
.init = uartmem_init,
.tx_byte = uartmem_tx_byte,
.rx_byte = uartmem_rx_byte,
.tst_byte = uartmem_tst_byte,
};

13
src/cpu/x86/smm/smiutil.c
View File

@ -26,7 +26,7 @@
#include <console/console.h>
#include <console/vtxprintf.h>
#if CONFIG_CONSOLE_SERIAL8250
#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
#include <uart8250.h>
#endif
#if CONFIG_USBDEBUG
@ -36,6 +36,10 @@
#include <console/ne2k.h>
#endif
#if CONFIG_CONSOLE_SERIAL8250MEM
static u32 serial8250mem_base_address = 0;
#endif
void console_tx_flush(void)
{
// the tx_byte functions take care of the flush.
@ -47,6 +51,10 @@ void console_tx_byte(unsigned char byte)
if (byte == '\n')
console_tx_byte('\r');
#if CONFIG_CONSOLE_SERIAL8250MEM
if (serial8250mem_base_address)
uart8250_mem_tx_byte(serial8250mem_base_address, byte);
#endif
#if CONFIG_CONSOLE_SERIAL8250
uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
#endif
@ -65,6 +73,9 @@ void console_init(void)
#if CONFIG_CONSOLE_SERIAL8250
uart_init();
#endif
#if CONFIG_CONSOLE_SERIAL8250MEM
serial8250mem_base_address = uart_mem_init();
#endif
#else
console_loglevel = 1;
#endif

1
src/drivers/Kconfig
View File

@ -22,6 +22,7 @@ source src/drivers/dec/Kconfig
source src/drivers/emulation/Kconfig
source src/drivers/generic/Kconfig
source src/drivers/i2c/Kconfig
source src/drivers/oxford/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/trident/Kconfig

1
src/drivers/Makefile.inc
View File

@ -22,6 +22,7 @@ subdirs-y += dec
subdirs-y += emulation
subdirs-y += generic
subdirs-y += i2c
subdirs-y += oxford
subdirs-y += sil
subdirs-y += trident

1
src/drivers/oxford/Kconfig Normal file
View File

@ -0,0 +1 @@
source src/drivers/oxford/oxpcie/Kconfig

1
src/drivers/oxford/Makefile.inc Normal file
View File

@ -0,0 +1 @@
subdirs-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie

68
src/drivers/oxford/oxpcie/Kconfig Normal file
View File

@ -0,0 +1,68 @@
config DRIVERS_OXFORD_OXPCIE
bool "Oxford OXPCIe952"
default n
select HAVE_UART_MEMORY_MAPPED
help
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
0xc158 will work.
NOTE: Right now you have to set the base address of your OXPCIe952
card to exactly the value that the device allocator would set them
later on, or serial console functionality will stop as soon as the
resource allocator assigns a new base address to the device.
config OXFORD_OXPCIE_BRIDGE_BUS
hex "OXPCIe's PCIe bridge bus number"
default 0x0
depends on DRIVERS_OXFORD_OXPCIE
help
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.
config OXFORD_OXPCIE_BRIDGE_DEVICE
hex "OXPCIe's PCIe bridge device number"
default 0x1c
depends on DRIVERS_OXFORD_OXPCIE
help
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.
config OXFORD_OXPCIE_BRIDGE_FUNCTION
hex "OXPCIe's PCIe bridge function number"
default 0x2
depends on DRIVERS_OXFORD_OXPCIE
help
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.
config OXFORD_OXPCIE_BRIDGE_SUBORDINATE
hex "OXPCIe's PCIe bridge subordinate bus"
default 0x3
depends on DRIVERS_OXFORD_OXPCIE
help
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.
config OXFORD_OXPCIE_BASE_ADDRESS
hex "Base address for rom stage console"
default 0xe0400000
depends on DRIVERS_OXFORD_OXPCIE
help
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
for the OXPCIe952 controller.

3
src/drivers/oxford/oxpcie/Makefile.inc Normal file
View File

@ -0,0 +1,3 @@
driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c
romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c

56
src/drivers/oxford/oxpcie/oxpcie.c Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include <arch/io.h>
#include <uart8250.h>
static void oxford_oxpcie_enable(device_t dev)
{
printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
struct resource *res = find_resource(dev, 0x10);
if (!res) {
printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
return;
}
printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
(read32(res->base) >> 8), (read32(res->base) & 0xff));
printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
(read32(res->base + 4) & 3));
}
static struct device_operations oxford_oxpcie_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = oxford_oxpcie_enable,
.scan_bus = 0,
};
static const struct pci_driver oxford_oxpcie_driver __pci_driver = {
.ops = &oxford_oxpcie_ops,
.vendor = 0x1415,
.device = 0xc158,
};

89
src/drivers/oxford/oxpcie/oxpcie_early.c Normal file
View File

@ -0,0 +1,89 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <uart8250.h>
#include <device/pci_def.h>
#define PCIE_BRIDGE \
PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \
CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \
CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
#define OXPCIE_DEVICE \
PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
void oxford_init(void)
{
u16 reg16;
/* First we reset the secondary bus */
reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
reg16 |= (1 << 6); /* SRESET */
pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
/* Assume we don't have to wait here forever */
/* Read back and clear reset bit. */
reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
reg16 &= ~(1 << 6); /* SRESET */
pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
/* Set up subordinate bus number */
pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00);
pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00);
pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS,
CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS,
CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
/* Memory window for the OXPCIe952 card */
// XXX is the calculation of base and limit corect?
pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
/* Enable memory access through bridge */
reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
// FIXME Add a timeout or this will hang forever if
// no device is in the slot.
u32 id = 0;
while ((id == 0) || (id == 0xffffffff))
id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
/* Setup base address on device */
pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
/* Enable memory on device */
reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
/* Now the UART initialization */
u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
}

1
src/include/boot/coreboot_tables.h
View File

@ -163,6 +163,7 @@ struct lb_console {
#define LB_TAG_CONSOLE_LOGBUF 3
#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
#define LB_TAG_CONSOLE_EHCI 5
#define LB_TAG_CONSOLE_SERIAL8250MEM 6
#define LB_TAG_FORWARD 0x0011
struct lb_forward {

12
src/include/uart8250.h
View File

@ -124,6 +124,7 @@
#define UART_MSR_DCTS 0x01 /* Delta CTS */
#define UART_SCR 0x07
#define UART_SPR 0x07
#ifndef __ROMCC__
@ -136,6 +137,17 @@ void uart8250_tx_byte(unsigned base_port, unsigned char data);
*/
void uart8250_init(unsigned base_port, unsigned divisor);
void uart_init(void);
/* and the same for memory mapped uarts */
unsigned char uart8250_mem_rx_byte(unsigned base_port);
int uart8250_mem_can_rx_byte(unsigned base_port);
void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
void uart8250_mem_init(unsigned base_port, unsigned divisor);
u32 uart_mem_init(void);
/* and special init for OXPCIe based cards */
void oxford_init(void);
#endif
#endif /* UART8250_H */

3
src/lib/Makefile.inc
View File

@ -9,6 +9,7 @@ romstage-y += lzma.c
romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
romstage-$(CONFIG_USBDEBUG) += usbdebug.c
@ -29,6 +30,7 @@ ramstage-y += gcc.c
ramstage-y += clog2.c
ramstage-y += cbmem.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
@ -36,5 +38,6 @@ driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
smm-y += memcpy.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
$(obj)/lib/version.ramstage.o : $(obj)/build.h

139
src/lib/uart8250mem.c Normal file
View File

@ -0,0 +1,139 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
* Copyright (C) 2006-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <uart8250.h>
#include <pc80/mc146818rtc.h>
#if CONFIG_USE_OPTION_TABLE
#include "option_table.h"
#endif
#if !defined(__SMM__) && !defined(__PRE_RAM__)
#include <device/device.h>
#endif
/* Should support 8250, 16450, 16550, 16550A type UARTs */
static inline int uart8250_mem_can_tx_byte(unsigned base_port)
{
return read8(base_port + UART_LSR) & UART_MSR_DSR;
}
static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port)
{
while(!uart8250_mem_can_tx_byte(base_port))
;
}
static inline void uart8250_mem_wait_until_sent(unsigned base_port)
{
while(!(read8(base_port + UART_LSR) & UART_LSR_TEMT))
;
}
void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
{
uart8250_mem_wait_to_tx_byte(base_port);
write8(base_port + UART_TBR, data);
/* Make certain the data clears the FIFOs */
uart8250_mem_wait_until_sent(base_port);
}
int uart8250_mem_can_rx_byte(unsigned base_port)
{
return read8(base_port + UART_LSR) & UART_LSR_DR;
}
unsigned char uart8250_mem_rx_byte(unsigned base_port)
{
while(!uart8250_mem_can_rx_byte(base_port))
;
return read8(base_port + UART_RBR);
}
void uart8250_mem_init(unsigned base_port, unsigned divisor)
{
/* Disable interrupts */
write8(base_port + UART_IER, 0x0);
/* Enable FIFOs */
write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
/* Assert DTR and RTS so the other end is happy */
write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
/* DLAB on */
write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
/* Set Baud Rate Divisor. 12 ==> 115200 Baud */
write8(base_port + UART_DLL, divisor & 0xFF);
write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
/* Set to 3 for 8N1 */
write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
}
u32 uart_mem_init(void)
{
unsigned uart_baud = CONFIG_TTYS0_BAUD;
u32 uart_bar = 0;
unsigned div;
/* find out the correct baud rate */
#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE
static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 };
unsigned b_index = 0;
#if defined(__PRE_RAM__)
b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
b_index &= 7;
uart_baud = baud[b_index];
#else
if (get_option(&b_index, "baud_rate") == 0) {
uart_baud = baud[b_index];
}
#endif
#endif
/* Now find the UART base address and calculate the divisor */
#if CONFIG_DRIVERS_OXFORD_OXPCIE
#if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__)
device_t dev = dev_find_device(0x1415, 0xc158, NULL);
if (dev) {
struct resource *res = find_resource(dev, 0x10);
if (res) {
uart_bar = res->base + 0x1000; // for 1st UART
// uart_bar = res->base + 0x2000; // for 2nd UART
}
}
if (!uart_bar)
#endif
uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART
// uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART
div = 4000000 / uart_baud;
#endif
if (uart_bar)
uart8250_mem_init(uart_bar, div);
return uart_bar;
}