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mb/google/zork: Move EC wake to happen in ramstage 

Currently, EC wake signal (GPIO_24) is configured early on in
romstage. However, there is no need for that since EC wake is not
really required to be configured until ramstage. This change moves
GPIO_24 configuration to happen in ramstage.

BUG=b:159832123

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42952
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-06-30 14:08:27 -07:00
parent ffbf5d9818
commit 489ffefef6
2 changed files with 4 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@ -12,8 +12,6 @@
static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* PEN_POWER_EN - reset */ /* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW), PAD_GPO(GPIO_5, LOW),
/* EC_FCH_WAKE_L */
PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
/* PCIE_RST1_L - Variable timings (May remove) */ /* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
@ -45,8 +43,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
PAD_GPO(GPIO_5, LOW), PAD_GPO(GPIO_5, LOW),
/* EN_PWR_TOUCHPAD_PS2 - reset */ /* EN_PWR_TOUCHPAD_PS2 - reset */
PAD_GPO(GPIO_6, LOW), PAD_GPO(GPIO_6, LOW),
/* EC_FCH_WAKE_L */
PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
/* PCIE_RST1_L - Variable timings (May remove) */ /* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
@ -109,6 +105,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
/* AC_PRES */ /* AC_PRES */
PAD_NF(GPIO_23, AC_PRES, PULL_UP), PAD_NF(GPIO_23, AC_PRES, PULL_UP),
/* EC_FCH_WAKE_L */
PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
/* EC_AP_INT_ODL (Sensor Framesync) */ /* EC_AP_INT_ODL (Sensor Framesync) */
PAD_GPI(GPIO_31, PULL_UP), PAD_GPI(GPIO_31, PULL_UP),
/* */ /* */

6
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@ -12,8 +12,6 @@
static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* PEN_POWER_EN - reset */ /* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW), PAD_GPO(GPIO_5, LOW),
/* EC_FCH_WAKE_L */
PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH), PAD_GPO(GPIO_40, HIGH),
/* EN_PWR_TOUCHPAD_PS2 - reset */ /* EN_PWR_TOUCHPAD_PS2 - reset */
@ -41,8 +39,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
PAD_GPO(GPIO_5, LOW), PAD_GPO(GPIO_5, LOW),
/* EN_PWR_TOUCHPAD_PS2 - reset */ /* EN_PWR_TOUCHPAD_PS2 - reset */
PAD_GPO(GPIO_13, LOW), PAD_GPO(GPIO_13, LOW),
/* EC_FCH_WAKE_L */
PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH), PAD_GPO(GPIO_40, HIGH),
/* EMMC_RESET - reset (default stuffing unused)*/ /* EMMC_RESET - reset (default stuffing unused)*/
@ -105,6 +101,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
/* AC_PRES */ /* AC_PRES */
PAD_NF(GPIO_23, AC_PRES, PULL_UP), PAD_NF(GPIO_23, AC_PRES, PULL_UP),
/* EC_FCH_WAKE_L */
PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
/* EC_AP_INT_ODL (Sensor Framesync) */ /* EC_AP_INT_ODL (Sensor Framesync) */
PAD_GPI(GPIO_31, PULL_UP), PAD_GPI(GPIO_31, PULL_UP),
/* EN_PWR_FP */ /* EN_PWR_FP */