mb/google/sarien: Modify SSD power sequence
Due to we turn off SSD power in S5. CB:32952 Based on M2 spec we have to turn on SSD power before RST assert. BUG=b:133389422 TEST=verify warm boot and cold boot are boot successfully. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/33029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -211,7 +211,6 @@ static const struct pad_config gpio_table[] = {
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/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
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/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
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/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
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/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
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/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
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@ -239,6 +238,7 @@ static const struct pad_config gpio_table[] = {
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* SSD RESET pin will stay low first */
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/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
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@ -197,7 +197,6 @@ static const struct pad_config gpio_table[] = {
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/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
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/* I2C5_SDA */ PAD_NC(GPP_H10, NONE),
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/* I2C5_SCL */ PAD_NC(GPP_H11, NONE),
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
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/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
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/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
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@ -224,6 +223,7 @@ static const struct pad_config gpio_table[] = {
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */
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/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
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