PCI ops: Define read-modify-write routines globally
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
parent
154768b902
commit
48c389e69e
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@ -374,4 +374,37 @@ void pci_or_config32(device_t dev, unsigned int where, u32 ormask)
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pci_write_config32(dev, where, value | ormask);
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}
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static inline __attribute__ ((always_inline))
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void pci_update_config8(device_t dev, int reg, u8 mask, u8 or)
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{
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u8 reg8;
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reg8 = pci_read_config8(dev, reg);
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reg8 &= mask;
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reg8 |= or;
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pci_write_config8(dev, reg, reg8);
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}
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static inline __attribute__ ((always_inline))
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void pci_update_config16(device_t dev, int reg, u16 mask, u16 or)
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{
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u16 reg16;
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reg16 = pci_read_config16(dev, reg);
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reg16 &= mask;
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reg16 |= or;
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pci_write_config16(dev, reg, reg16);
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}
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static inline __attribute__ ((always_inline))
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void pci_update_config32(device_t dev, int reg, u32 mask, u32 or)
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{
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u32 reg32;
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reg32 = pci_read_config32(dev, reg);
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reg32 &= mask;
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reg32 |= or;
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pci_write_config32(dev, reg, reg32);
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}
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#endif
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@ -122,16 +122,6 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
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pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
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}
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
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{
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u32 reg32;
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reg32 = pci_read_config32(dev, reg);
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reg32 &= mask;
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reg32 |= or;
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pci_write_config32(dev, reg, reg32);
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}
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static void pciexp_config_max_latency(device_t root, device_t dev)
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{
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unsigned int cap;
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@ -150,7 +140,7 @@ static void pciexp_enable_ltr(device_t dev)
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dev_path(dev));
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return;
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}
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pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10);
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pci_update_config32(dev, cap + 0x28, ~(1 << 10), 1 << 10);
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}
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static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap,
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@ -226,26 +216,26 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev,
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pciexp_enable_ltr(root);
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pcie_update_cfg(root, root_cap + 0x08, ~0xff00,
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pci_update_config32(root, root_cap + 0x08, ~0xff00,
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(comm_mode_rst_time << 8));
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pcie_update_cfg(root, root_cap + 0x0c , 0xffffff04,
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pci_update_config32(root, root_cap + 0x0c , 0xffffff04,
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(endp_power_on_value << 3) | (power_on_scale));
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pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000,
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pci_update_config32(root, root_cap + 0x08, ~0xe3ff0000,
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(1 << 21) | (1 << 23) | (1 << 30));
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pcie_update_cfg(root, root_cap + 0x08, ~0x1f,
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pci_update_config32(root, root_cap + 0x08, ~0x1f,
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L1SubStateSupport);
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for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
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pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04,
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pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04,
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(endp_power_on_value << 3) | (power_on_scale));
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pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000,
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pci_update_config32(dev_t, end_cap + 0x08, ~0xe3ff0000,
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(1 << 21) | (1 << 23) | (1 << 30));
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pcie_update_cfg(dev_t, end_cap + 0x08, ~0x1f,
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pci_update_config32(dev_t, end_cap + 0x08, ~0x1f,
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L1SubStateSupport);
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pciexp_enable_ltr(dev_t);
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@ -30,9 +30,6 @@
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#include <soc/cpu.h>
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#include <delay.h>
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static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
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/* Low Power variant has 6 root ports. */
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#define NUM_ROOT_PORTS 6
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@ -129,14 +126,14 @@ static void root_port_init_config(device_t dev)
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rpc.num_ports = NUM_ROOT_PORTS;
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rpc.gbe_port = -1;
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/* RP0 f5[3:0] = 0101b*/
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pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5);
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pci_update_config8(dev, 0xf5, ~0xa, 0x5);
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pcie_iosf_port_grant_count(dev);
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rpc.pin_ownership = pci_read_config32(dev, 0x410);
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root_port_config_update_gbe_port();
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pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4));
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pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
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if (dev->chip_info != NULL) {
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config_t *config = dev->chip_info;
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rpc.coalesce = config->pcie_port_coalesce;
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@ -168,7 +165,7 @@ static void root_port_init_config(device_t dev)
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break;
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}
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pcie_update_cfg(dev, 0x418, 0, 0x02000430);
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pci_update_config32(dev, 0x418, 0, 0x02000430);
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if (root_port_is_first(dev)) {
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/*
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@ -227,23 +224,23 @@ static void pcie_enable_clock_gating(void)
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if (!dev->enabled) {
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/* Configure shared resource clock gating. */
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if (rp == 1 || rp == 5 || rp == 6)
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pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c);
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pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
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pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4));
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pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31));
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pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
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pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));
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/* Per-Port CLKREQ# handling. */
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if (gpio_is_native(18 + rp - 1))
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pcie_update_cfg(dev, 0x420, ~0, (3 << 29));
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pci_update_config32(dev, 0x420, ~0, (3 << 29));
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/* Enable static clock gating. */
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if (rp == 1 && !rpc.ports[1]->enabled &&
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!rpc.ports[2]->enabled && !rpc.ports[3]->enabled) {
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pcie_update_cfg8(dev, 0xe2, ~1, 1);
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pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80);
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pci_update_config8(dev, 0xe2, ~1, 1);
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pci_update_config8(dev, 0xe1, 0x7f, 0x80);
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} else if (rp == 5 || rp == 6) {
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pcie_update_cfg8(dev, 0xe2, ~1, 1);
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pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80);
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pci_update_config8(dev, 0xe2, ~1, 1);
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pci_update_config8(dev, 0xe1, 0x7f, 0x80);
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}
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continue;
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}
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@ -251,17 +248,17 @@ static void pcie_enable_clock_gating(void)
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enabled_ports++;
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/* Enable dynamic clock gating. */
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pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03);
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pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6));
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pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2));
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pci_update_config8(dev, 0xe1, 0xfc, 0x03);
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pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6));
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pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2));
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/* Update PECR1 register. */
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pcie_update_cfg8(dev, 0xe8, ~0, 3);
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pci_update_config8(dev, 0xe8, ~0, 3);
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if (is_broadwell) {
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pcie_update_cfg(dev, 0x324, ~((1 << 5) | (1 << 14)),
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pci_update_config32(dev, 0x324, ~((1 << 5) | (1 << 14)),
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((1 << 5) | (1 << 14)));
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} else {
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pcie_update_cfg(dev, 0x324, ~(1 << 5), (1 << 5));
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pci_update_config32(dev, 0x324, ~(1 << 5), (1 << 5));
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}
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/* Per-Port CLKREQ# handling. */
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if (gpio_is_native(18 + rp - 1))
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@ -269,18 +266,18 @@ static void pcie_enable_clock_gating(void)
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* In addition to D28Fx PCICFG 420h[30:29] = 11b,
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* set 420h[17] = 0b and 420[0] = 1b for L1 SubState.
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*/
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pcie_update_cfg(dev, 0x420, ~0x20000, (3 << 29) | 1);
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pci_update_config32(dev, 0x420, ~0x20000, (3 << 29) | 1);
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/* Configure shared resource clock gating. */
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if (rp == 1 || rp == 5 || rp == 6)
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pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c);
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pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
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/* CLKREQ# VR Idle Enable */
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RCBA32_OR(0x2b1c, (1 << (16 + i)));
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}
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if (!enabled_ports)
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pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6));
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pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6));
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}
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static void root_port_commit_config(void)
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@ -312,7 +309,7 @@ static void root_port_commit_config(void)
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printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
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/* 8.2 Configuration of PCI Express Root Ports */
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pcie_update_cfg(dev, 0x338, ~(1 << 26), 1 << 26);
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pci_update_config32(dev, 0x338, ~(1 << 26), 1 << 26);
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do {
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reg32 = pci_read_config32(dev, 0x328);
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@ -326,7 +323,7 @@ static void root_port_commit_config(void)
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printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
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dev_path(dev));
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pcie_update_cfg(dev, 0x408, ~(1 << 27), 1 << 27);
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pci_update_config32(dev, 0x408, ~(1 << 27), 1 << 27);
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/* Disable this device if possible */
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pch_disable_devfn(dev);
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@ -439,26 +436,6 @@ static void root_port_check_disable(device_t dev)
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}
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}
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static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or)
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{
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u8 reg8;
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reg8 = pci_read_config8(dev, reg);
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reg8 &= mask;
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reg8 |= or;
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pci_write_config8(dev, reg, reg8);
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}
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
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{
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u32 reg32;
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reg32 = pci_read_config32(dev, reg);
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reg32 &= mask;
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reg32 |= or;
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pci_write_config32(dev, reg, reg32);
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}
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static void pcie_add_0x0202000_iobp(u32 reg)
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{
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u32 reg32;
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@ -510,10 +487,10 @@ static void pch_pcie_early(struct device *dev)
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if (do_aspm) {
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/* Set ASPM bits in MPC2 register. */
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pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
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pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
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/* Set unique clock exit latency in MPC register. */
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pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
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pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
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switch (rp) {
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case 1:
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@ -547,55 +524,55 @@ static void pch_pcie_early(struct device *dev)
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break;
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}
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pcie_update_cfg(dev, 0x338, ~(1 << 26), 0);
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pci_update_config32(dev, 0x338, ~(1 << 26), 0);
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}
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/* Enable LTR in Root Port. Disable OBFF. */
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pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
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pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10));
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pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
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pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
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pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
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pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
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/* Set L1 exit latency in LCAP register. */
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if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
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pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
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pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
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else
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pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
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pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
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pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b);
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pci_update_config32(dev, 0x314, 0x0, 0x743a361b);
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/* Set Common Clock Exit Latency in MPC register. */
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pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
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pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
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pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854d74);
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pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74);
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/* Set Invalid Receive Range Check Enable in MPC register. */
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pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));
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pci_update_config32(dev, 0xd8, ~0, (1 << 25));
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pcie_update_cfg8(dev, 0xf5, 0x0f, 0);
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pci_update_config8(dev, 0xf5, 0x0f, 0);
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/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
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pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
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pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
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/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
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pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e);
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pci_update_config32(dev, 0x200, ~0xffff, 0x001e);
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pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6),
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pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6),
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(1 << 20) | (3 << 6));
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/* Enable Relaxed Order from Root Port. */
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pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23));
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pci_update_config32(dev, 0x320, ~(3 << 23), (3 << 23));
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if (rp == 1 || rp == 5 || rp == 6)
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pcie_update_cfg8(dev, 0xf7, ~0xc, 0);
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pci_update_config8(dev, 0xf7, ~0xc, 0);
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/* Set EOI forwarding disable. */
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pcie_update_cfg(dev, 0xd4, ~0, (1 << 1));
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pci_update_config32(dev, 0xd4, ~0, (1 << 1));
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/* Read and write back write-once capability registers. */
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pcie_update_cfg(dev, 0x34, ~0, 0);
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pcie_update_cfg(dev, 0x40, ~0, 0);
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pcie_update_cfg(dev, 0x80, ~0, 0);
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pcie_update_cfg(dev, 0x90, ~0, 0);
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pci_update_config32(dev, 0x34, ~0, 0);
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pci_update_config32(dev, 0x40, ~0, 0);
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pci_update_config32(dev, 0x80, ~0, 0);
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pci_update_config32(dev, 0x90, ~0, 0);
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}
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static void pch_pcie_init(struct device *dev)
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@ -131,16 +131,6 @@ static void pch_enable_lpc(void)
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pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
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}
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
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{
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u32 reg32;
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reg32 = pci_read_config32(dev, reg);
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reg32 &= mask;
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reg32 |= or;
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pci_write_config32(dev, reg, reg32);
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}
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void pch_early_init(void)
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{
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reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
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@ -151,7 +141,7 @@ void pch_early_init(void)
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enable_smbus();
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/* 8.14 Additional PCI Express Programming Steps, step #1 */
|
||||
pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0);
|
||||
pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80);
|
||||
pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30);
|
||||
pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0);
|
||||
pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80);
|
||||
pci_update_config32(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,9 +22,6 @@
|
|||
#include "pch.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
|
||||
static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
|
||||
|
||||
/* LynxPoint-LP has 6 root ports while non-LP has 8. */
|
||||
#define MAX_NUM_ROOT_PORTS 8
|
||||
#define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS
|
||||
|
|
@ -198,39 +195,39 @@ static void pcie_enable_clock_gating(void)
|
|||
if (!dev->enabled) {
|
||||
/* Configure shared resource clock gating. */
|
||||
if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
|
||||
pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c);
|
||||
pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
|
||||
|
||||
if (!is_lp) {
|
||||
if (rp == 1 && !rpc.ports[1]->enabled &&
|
||||
!rpc.ports[2]->enabled &&
|
||||
!rpc.ports[3]->enabled) {
|
||||
pcie_update_cfg8(dev, 0xe2, ~1, 1);
|
||||
pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80);
|
||||
pci_update_config8(dev, 0xe2, ~1, 1);
|
||||
pci_update_config8(dev, 0xe1, 0x7f, 0x80);
|
||||
}
|
||||
if (rp == 5 && !rpc.ports[5]->enabled &&
|
||||
!rpc.ports[6]->enabled &&
|
||||
!rpc.ports[7]->enabled) {
|
||||
pcie_update_cfg8(dev, 0xe2, ~1, 1);
|
||||
pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80);
|
||||
pci_update_config8(dev, 0xe2, ~1, 1);
|
||||
pci_update_config8(dev, 0xe1, 0x7f, 0x80);
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4));
|
||||
pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31));
|
||||
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
|
||||
pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));
|
||||
|
||||
/* Per-Port CLKREQ# handling. */
|
||||
if (is_lp && gpio_is_native(18 + rp - 1))
|
||||
pcie_update_cfg(dev, 0x420, ~0, (3 << 29));
|
||||
pci_update_config32(dev, 0x420, ~0, (3 << 29));
|
||||
|
||||
/* Enable static clock gating. */
|
||||
if (rp == 1 && !rpc.ports[1]->enabled &&
|
||||
!rpc.ports[2]->enabled && !rpc.ports[3]->enabled) {
|
||||
pcie_update_cfg8(dev, 0xe2, ~1, 1);
|
||||
pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80);
|
||||
pci_update_config8(dev, 0xe2, ~1, 1);
|
||||
pci_update_config8(dev, 0xe1, 0x7f, 0x80);
|
||||
} else if (rp == 5 || rp == 6) {
|
||||
pcie_update_cfg8(dev, 0xe2, ~1, 1);
|
||||
pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80);
|
||||
pci_update_config8(dev, 0xe2, ~1, 1);
|
||||
pci_update_config8(dev, 0xe1, 0x7f, 0x80);
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
|
@ -238,29 +235,29 @@ static void pcie_enable_clock_gating(void)
|
|||
enabled_ports++;
|
||||
|
||||
/* Enable dynamic clock gating. */
|
||||
pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03);
|
||||
pci_update_config8(dev, 0xe1, 0xfc, 0x03);
|
||||
|
||||
if (is_lp) {
|
||||
pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6));
|
||||
pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2));
|
||||
pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6));
|
||||
pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2));
|
||||
}
|
||||
|
||||
/* Update PECR1 register. */
|
||||
pcie_update_cfg8(dev, 0xe8, ~0, 1);
|
||||
pci_update_config8(dev, 0xe8, ~0, 1);
|
||||
|
||||
pcie_update_cfg8(dev, 0x324, ~(1 << 5), (1 < 5));
|
||||
pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5));
|
||||
|
||||
/* Per-Port CLKREQ# handling. */
|
||||
if (is_lp && gpio_is_native(18 + rp - 1))
|
||||
pcie_update_cfg(dev, 0x420, ~0, (3 << 29));
|
||||
pci_update_config32(dev, 0x420, ~0, (3 << 29));
|
||||
|
||||
/* Configure shared resource clock gating. */
|
||||
if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
|
||||
pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c);
|
||||
pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
|
||||
}
|
||||
|
||||
if (!enabled_ports && is_lp)
|
||||
pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6));
|
||||
pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6));
|
||||
}
|
||||
|
||||
static void root_port_commit_config(void)
|
||||
|
|
@ -458,26 +455,6 @@ static void root_port_check_disable(device_t dev)
|
|||
}
|
||||
}
|
||||
|
||||
static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
reg8 = pci_read_config8(dev, reg);
|
||||
reg8 &= mask;
|
||||
reg8 |= or;
|
||||
pci_write_config8(dev, reg, reg8);
|
||||
}
|
||||
|
||||
static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = pci_read_config32(dev, reg);
|
||||
reg32 &= mask;
|
||||
reg32 |= or;
|
||||
pci_write_config32(dev, reg, reg32);
|
||||
}
|
||||
|
||||
static void pcie_add_0x0202000_iobp(u32 reg)
|
||||
{
|
||||
u32 reg32;
|
||||
|
|
@ -549,13 +526,13 @@ static void pch_pcie_early(struct device *dev)
|
|||
|
||||
if (do_aspm) {
|
||||
/* Set ASPM bits in MPC2 register. */
|
||||
pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
|
||||
pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
|
||||
|
||||
/* Set unique clock exit latency in MPC register. */
|
||||
pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
|
||||
pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
|
||||
|
||||
/* Set L1 exit latency in LCAP register. */
|
||||
pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
|
||||
pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
|
||||
|
||||
if (is_lp) {
|
||||
switch (rp) {
|
||||
|
|
@ -624,50 +601,50 @@ static void pch_pcie_early(struct device *dev)
|
|||
}
|
||||
}
|
||||
|
||||
pcie_update_cfg(dev, 0x338, ~(1 << 26), 0);
|
||||
pci_update_config32(dev, 0x338, ~(1 << 26), 0);
|
||||
}
|
||||
|
||||
/* Enable LTR in Root Port. */
|
||||
pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11));
|
||||
pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10));
|
||||
pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11));
|
||||
pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
|
||||
|
||||
pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
|
||||
pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
|
||||
|
||||
/* Set L1 exit latency in LCAP register. */
|
||||
if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
|
||||
pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
|
||||
pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
|
||||
else
|
||||
pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
|
||||
pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
|
||||
|
||||
pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b);
|
||||
pci_update_config32(dev, 0x314, 0x0, 0x743a361b);
|
||||
|
||||
/* Set Common Clock Exit Latency in MPC register. */
|
||||
pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
|
||||
pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
|
||||
|
||||
pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74);
|
||||
pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74);
|
||||
|
||||
/* Set Invalid Recieve Range Check Enable in MPC register. */
|
||||
pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));
|
||||
pci_update_config32(dev, 0xd8, ~0, (1 << 25));
|
||||
|
||||
pcie_update_cfg8(dev, 0xf5, 0x3f, 0);
|
||||
pci_update_config8(dev, 0xf5, 0x3f, 0);
|
||||
|
||||
if (rp == 1 || rp == 5 || (is_lp && rp == 6))
|
||||
pcie_update_cfg8(dev, 0xf7, ~0xc, 0);
|
||||
pci_update_config8(dev, 0xf7, ~0xc, 0);
|
||||
|
||||
/* Set EOI forwarding disable. */
|
||||
pcie_update_cfg(dev, 0xd4, ~0, (1 << 1));
|
||||
pci_update_config32(dev, 0xd4, ~0, (1 << 1));
|
||||
|
||||
/* Set something involving advanced error reporting. */
|
||||
pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001);
|
||||
pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001);
|
||||
|
||||
if (is_lp)
|
||||
pcie_update_cfg(dev, 0x100, ~0, (1 << 29));
|
||||
pci_update_config32(dev, 0x100, ~0, (1 << 29));
|
||||
|
||||
/* Read and write back write-once capability registers. */
|
||||
pcie_update_cfg(dev, 0x34, ~0, 0);
|
||||
pcie_update_cfg(dev, 0x40, ~0, 0);
|
||||
pcie_update_cfg(dev, 0x80, ~0, 0);
|
||||
pcie_update_cfg(dev, 0x90, ~0, 0);
|
||||
pci_update_config32(dev, 0x34, ~0, 0);
|
||||
pci_update_config32(dev, 0x40, ~0, 0);
|
||||
pci_update_config32(dev, 0x80, ~0, 0);
|
||||
pci_update_config32(dev, 0x90, ~0, 0);
|
||||
}
|
||||
|
||||
static void pci_init(struct device *dev)
|
||||
|
|
|
|||
Loading…
Reference in New Issue